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Kiyohiro NOGUCHI, Yumiko KAWASHIMA, Shinya NARITA, "A Highly Reliable Frame-Relay Switching Node Architecture Based on ATM Switching Technology" in IEICE TRANSACTIONS on Communications,
vol. E81-B, no. 2, pp. 315-323, February 1998, doi: .
Abstract: Local Area Networks(LANs)are now being used all over the world. The need for cost-effective and high-speed communication services, such as LAN interconnections and large-volume file transfer of all types of data is rapidly increasing. At the same time, Internet services are spreading rapidly, and well soon see the construction of a cost-effective open computer network (OCN). Frame-relay and cell-relay technologies which can achieve higher-speed and higher-performance switching than packet switching, are therefore attracting much attention. Frame-relay technologies are also important because they provide an infrastructure for high-speed data communication as fast as 1. 5 Mbit/sec. Demand for these frame-relay network services have been increasing rapidly. We propose a cost-effective and highly reliable node architecture that we have developed at NTT. Our basic concept for this is based on the all-band switching node architecture which can provide both STM and ATM switches on the same hardware and software platforms, and can accommodate any type of node, such as STM nodes, and ATM nodes for B-ISDN. Our proposed architecture forms highly reliable frame-relay network infrastructure. By using a scale-flexibility building-block architecture, we can construct a small-scale node and a large-scale node cost-effectively. Next, the key technologies of highly reliable node architecture are presented. These are methods of changing over following function-units without frame-loss and/or cell-loss. We present two examples: frame-relay protocol processing units(PPUs)with an N+M-redundant architecture that consists of a number of acting PPUs(ACT)and a number of standby PPUs(SBY)waiting to become active, and duplicate ATM Mux/DemuX blocks(ATM MDXs)with a cell shaping buffer.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e81-b_2_315/_p
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@ARTICLE{e81-b_2_315,
author={Kiyohiro NOGUCHI, Yumiko KAWASHIMA, Shinya NARITA, },
journal={IEICE TRANSACTIONS on Communications},
title={A Highly Reliable Frame-Relay Switching Node Architecture Based on ATM Switching Technology},
year={1998},
volume={E81-B},
number={2},
pages={315-323},
abstract={Local Area Networks(LANs)are now being used all over the world. The need for cost-effective and high-speed communication services, such as LAN interconnections and large-volume file transfer of all types of data is rapidly increasing. At the same time, Internet services are spreading rapidly, and well soon see the construction of a cost-effective open computer network (OCN). Frame-relay and cell-relay technologies which can achieve higher-speed and higher-performance switching than packet switching, are therefore attracting much attention. Frame-relay technologies are also important because they provide an infrastructure for high-speed data communication as fast as 1. 5 Mbit/sec. Demand for these frame-relay network services have been increasing rapidly. We propose a cost-effective and highly reliable node architecture that we have developed at NTT. Our basic concept for this is based on the all-band switching node architecture which can provide both STM and ATM switches on the same hardware and software platforms, and can accommodate any type of node, such as STM nodes, and ATM nodes for B-ISDN. Our proposed architecture forms highly reliable frame-relay network infrastructure. By using a scale-flexibility building-block architecture, we can construct a small-scale node and a large-scale node cost-effectively. Next, the key technologies of highly reliable node architecture are presented. These are methods of changing over following function-units without frame-loss and/or cell-loss. We present two examples: frame-relay protocol processing units(PPUs)with an N+M-redundant architecture that consists of a number of acting PPUs(ACT)and a number of standby PPUs(SBY)waiting to become active, and duplicate ATM Mux/DemuX blocks(ATM MDXs)with a cell shaping buffer.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A Highly Reliable Frame-Relay Switching Node Architecture Based on ATM Switching Technology
T2 - IEICE TRANSACTIONS on Communications
SP - 315
EP - 323
AU - Kiyohiro NOGUCHI
AU - Yumiko KAWASHIMA
AU - Shinya NARITA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E81-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 1998
AB - Local Area Networks(LANs)are now being used all over the world. The need for cost-effective and high-speed communication services, such as LAN interconnections and large-volume file transfer of all types of data is rapidly increasing. At the same time, Internet services are spreading rapidly, and well soon see the construction of a cost-effective open computer network (OCN). Frame-relay and cell-relay technologies which can achieve higher-speed and higher-performance switching than packet switching, are therefore attracting much attention. Frame-relay technologies are also important because they provide an infrastructure for high-speed data communication as fast as 1. 5 Mbit/sec. Demand for these frame-relay network services have been increasing rapidly. We propose a cost-effective and highly reliable node architecture that we have developed at NTT. Our basic concept for this is based on the all-band switching node architecture which can provide both STM and ATM switches on the same hardware and software platforms, and can accommodate any type of node, such as STM nodes, and ATM nodes for B-ISDN. Our proposed architecture forms highly reliable frame-relay network infrastructure. By using a scale-flexibility building-block architecture, we can construct a small-scale node and a large-scale node cost-effectively. Next, the key technologies of highly reliable node architecture are presented. These are methods of changing over following function-units without frame-loss and/or cell-loss. We present two examples: frame-relay protocol processing units(PPUs)with an N+M-redundant architecture that consists of a number of acting PPUs(ACT)and a number of standby PPUs(SBY)waiting to become active, and duplicate ATM Mux/DemuX blocks(ATM MDXs)with a cell shaping buffer.
ER -
English
