A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an inter-segment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alpha-tuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Tae-Joon KIM, Byung-Cheol SHIN, Dong-Ho CHO, "ELDQDB-SR: An Enhanced Loop Architecture of DQDB with Slot Reuse" in IEICE TRANSACTIONS on Communications,
vol. E82-B, no. 7, pp. 1019-1029, July 1999, doi: .
Abstract: A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an inter-segment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alpha-tuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e82-b_7_1019/_p
Copy
@ARTICLE{e82-b_7_1019,
author={Tae-Joon KIM, Byung-Cheol SHIN, Dong-Ho CHO, },
journal={IEICE TRANSACTIONS on Communications},
title={ELDQDB-SR: An Enhanced Loop Architecture of DQDB with Slot Reuse},
year={1999},
volume={E82-B},
number={7},
pages={1019-1029},
abstract={A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an inter-segment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alpha-tuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - ELDQDB-SR: An Enhanced Loop Architecture of DQDB with Slot Reuse
T2 - IEICE TRANSACTIONS on Communications
SP - 1019
EP - 1029
AU - Tae-Joon KIM
AU - Byung-Cheol SHIN
AU - Dong-Ho CHO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E82-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 1999
AB - A loop architecture of DQDB with slot reuse (LDQDB-SR) segmented by erasure nodes was studied to overcome the performance limitation due to the nature of the unidirectional bus architecture of DQDB with slot reuse. The LDQDB-SR adopts the destination slot release and an inter-segment bandwidth regulation based on the distributed queuing system of DQDB. This network suffers not only from severe throughput deterioration due to a high regulation cost and an excessive transit delay but also from unfairness in bandwidth sharing, especially under an overload condition. In this paper, we introduce an enhanced loop architecture of DQDB with slot reuse (ELDQDB-SR) to improve the performance of LDQDB-SR. The ELDQDB-SR uses a quota-based inter-segment bandwidth regulation mechanism to effectively control the bandwidth use of each segment. Each station selects the bus that minimizes the number of erasure nodes on the path to destination stations. Fairness control methods of DQDB are reviewed and the alpha-tuning mechanism is modified to achieve a fair bandwidth distribution among stations within each segment. Simulation results show that the ELDQDB-SR gives an enhanced throughput level and also maintains good fairness under overload conditions.
ER -