IEICE TRANSACTIONS on Communications
Ethernet Over HDLC Forwarding VLSI for Network Access System
Summary :
In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E85-B No.7 pp.1382-1385
- Publication Date
- 2002/07/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- Communication Devices/Circuits
Authors
Keyword
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Minsuk HONG, Jinsung OH, Chan Young PARK, Wooseok KANG, Sehyeon RHEE, Sang-Hui PARK, "Ethernet Over HDLC Forwarding VLSI for Network Access System" in IEICE TRANSACTIONS on Communications,
vol. E85-B, no. 7, pp. 1382-1385, July 2002, doi: .
Abstract: In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e85-b_7_1382/_p
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@ARTICLE{e85-b_7_1382,
author={Minsuk HONG, Jinsung OH, Chan Young PARK, Wooseok KANG, Sehyeon RHEE, Sang-Hui PARK, },
journal={IEICE TRANSACTIONS on Communications},
title={Ethernet Over HDLC Forwarding VLSI for Network Access System},
year={2002},
volume={E85-B},
number={7},
pages={1382-1385},
abstract={In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Ethernet Over HDLC Forwarding VLSI for Network Access System
T2 - IEICE TRANSACTIONS on Communications
SP - 1382
EP - 1385
AU - Minsuk HONG
AU - Jinsung OH
AU - Chan Young PARK
AU - Wooseok KANG
AU - Sehyeon RHEE
AU - Sang-Hui PARK
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E85-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 2002
AB - In this paper, we present the design and implementation of a cost effective Ethernet over HDLC forwarding VLSI for network access system. It supports 10/100 Mbps Ethernet PHYs and up to 50 Mbps HDLC interface directly applied to Modem or transceiver. The maximum forwarding/filtering rate is 90,000 pps with a throughput latency of 1 frame, which supports high speed applications. It can also support both master mode for Ethernet PHY and slave mode for switching chip by the pin configuration. It has been implemented as a single chip based on 0.5 µm CMOS technology. Field test shows that the wire-speed packet forwarding and processing using by the implemented chip can be achieved.
ER -
English
