IEICE TRANSACTIONS on Communications
Design of Buffer Controller for Flow-Based High Quality Communications
Summary :
As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.
- Publication
- IEICE TRANSACTIONS on Communications Vol.E86-B No.2 pp.655-663
- Publication Date
- 2003/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Internet Technology III)
- Category
- Packet Transmission
Authors
Keyword
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Katsuya MINAMI, Hideki TODE, Koso MURAKAMI, "Design of Buffer Controller for Flow-Based High Quality Communications" in IEICE TRANSACTIONS on Communications,
vol. E86-B, no. 2, pp. 655-663, February 2003, doi: .
Abstract: As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e86-b_2_655/_p
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@ARTICLE{e86-b_2_655,
author={Katsuya MINAMI, Hideki TODE, Koso MURAKAMI, },
journal={IEICE TRANSACTIONS on Communications},
title={Design of Buffer Controller for Flow-Based High Quality Communications},
year={2003},
volume={E86-B},
number={2},
pages={655-663},
abstract={As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - Design of Buffer Controller for Flow-Based High Quality Communications
T2 - IEICE TRANSACTIONS on Communications
SP - 655
EP - 663
AU - Katsuya MINAMI
AU - Hideki TODE
AU - Koso MURAKAMI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E86-B
IS - 2
JA - IEICE TRANSACTIONS on Communications
Y1 - February 2003
AB - As multimedia and high-speed traffic become more popular on the Internet, the various traffic requiring different qualities of service (QoS) must co-exist. In addition, classified services based on Diff-Serv (Differentiated Service), MPLS (Multi-Protocol Label Switching), etc., have come into wide use. Today's Internet environment requires routers to perform control mechanisms in order to guarantee various QoSs. In this paper, we propose a smart buffer management scheme for the Internet router that uses hierarchical priority control with port class and flow level. Furthermore, since the proposed scheme must operate at very high speed, we first propose several design policy for high speed operation and the hardware implementation is performed in VHDL code. Implementation results show that the proposed scheme can scale with high-speed link, achieving the maximum rate of 4.0 Gbps by using the 3.5 µm CMOS technology.
ER -
English
