IEICE TRANSACTIONS on Electronics
A New Low Power Test Pattern Generator for BIST Architecture
Summary :
A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E88-C No.10 pp.2037-2038
- Publication Date
- 2005/10/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietele/e88-c.10.2037
- Type of Manuscript
- LETTER
- Category
- Semiconductor Materials and Devices
Authors
Keyword
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Kicheol KIM, Dongsub SONG, Incheol KIM, Sungho KANG, "A New Low Power Test Pattern Generator for BIST Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 10, pp. 2037-2038, October 2005, doi: 10.1093/ietele/e88-c.10.2037.
Abstract: A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.10.2037/_p
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@ARTICLE{e88-c_10_2037,
author={Kicheol KIM, Dongsub SONG, Incheol KIM, Sungho KANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A New Low Power Test Pattern Generator for BIST Architecture},
year={2005},
volume={E88-C},
number={10},
pages={2037-2038},
abstract={A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.},
keywords={},
doi={10.1093/ietele/e88-c.10.2037},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - A New Low Power Test Pattern Generator for BIST Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 2037
EP - 2038
AU - Kicheol KIM
AU - Dongsub SONG
AU - Incheol KIM
AU - Sungho KANG
PY - 2005
DO - 10.1093/ietele/e88-c.10.2037
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2005
AB - A new low power test pattern generator (TPG) which can effectively reduce the average power consumption during test application is developed. The new TPG reduces the weighted switching activity (WSA) of the circuit under test (CUT) by suppressing transitions at some primary inputs which make many transitions. Moreover, the new TPG does not lose fault coverage. Experimental results on the ISCAS benchmark circuits show that average power reduction can be achieved up to 33.8% while achieving high fault coverage.
ER -
English
