An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs

Kenji SHIMAZAKI; Makoto NAGATA; Mitsuya FUKAZAWA; Shingo MIYAHARA; Masaaki HIRATA; Kazuhiro SATOH; Hiroyuki TSUJIKAWA

doi:10.1093/ietele/e89-c.11.1535

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs

Kenji SHIMAZAKI, Makoto NAGATA, Mitsuya FUKAZAWA, Shingo MIYAHARA, Masaaki HIRATA, Kazuhiro SATOH, Hiroyuki TSUJIKAWA

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We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1535-1543

Publication Date: 2006/11/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.11.1535

Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)

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Kenji SHIMAZAKI, Makoto NAGATA, Mitsuya FUKAZAWA, Shingo MIYAHARA, Masaaki HIRATA, Kazuhiro SATOH, Hiroyuki TSUJIKAWA, "An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 11, pp. 1535-1543, November 2006, doi: 10.1093/ietele/e89-c.11.1535.
Abstract: We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1535/_p

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@ARTICLE{e89-c_11_1535,
author={Kenji SHIMAZAKI, Makoto NAGATA, Mitsuya FUKAZAWA, Shingo MIYAHARA, Masaaki HIRATA, Kazuhiro SATOH, Hiroyuki TSUJIKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs},
year={2006},
volume={E89-C},
number={11},
pages={1535-1543},
abstract={We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.},
keywords={},
doi={10.1093/ietele/e89-c.11.1535},
ISSN={1745-1353},
month={November},}

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TY - JOUR
TI - An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1535
EP - 1543
AU - Kenji SHIMAZAKI
AU - Makoto NAGATA
AU - Mitsuya FUKAZAWA
AU - Shingo MIYAHARA
AU - Masaaki HIRATA
AU - Kazuhiro SATOH
AU - Hiroyuki TSUJIKAWA
PY - 2006
DO - 10.1093/ietele/e89-c.11.1535
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - We propose a semi-dynamic timing analysis flow applicable to large-scale circuits that takes into account dynamic power-supply drop. Logic delay is accurately estimated in the presence of power-supply noise through timing correction as a function of power-supply voltage during operation, where a time-dependent power-supply noise waveform is derived by way of a vectorless technique. Measurements and analysis of dynamic supply-noise waveforms and associated delay changes were performed on a sub-100-nm CMOS test circuit with embedded on-chip noise detectors and delay monitors. The proposed analysis technique was extended and applied to a test digital circuit with more than 10 million gates and validated toward a multi-10-million-gate CMOS SoC design.
ER -