Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic

Michitaka OKUNO; Shinji NISHIMURA; Shin-ichi ISHIDA; Hiroaki NISHI

doi:10.1093/ietele/e89-c.11.1620

Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic

Michitaka OKUNO, Shinji NISHIMURA, Shin-ichi ISHIDA, Hiroaki NISHI

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A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.

Publication: IEICE TRANSACTIONS on Electronics Vol.E89-C No.11 pp.1620-1628

Publication Date: 2006/11/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e89-c.11.1620

Type of Manuscript: Special Section PAPER (Special Section on Novel Device Architectures and System Integration Technologies)

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Michitaka OKUNO, Shinji NISHIMURA, Shin-ichi ISHIDA, Hiroaki NISHI, "Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic" in IEICE TRANSACTIONS on Electronics, vol. E89-C, no. 11, pp. 1620-1628, November 2006, doi: 10.1093/ietele/e89-c.11.1620.
Abstract: A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.11.1620/_p

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@ARTICLE{e89-c_11_1620,
author={Michitaka OKUNO, Shinji NISHIMURA, Shin-ichi ISHIDA, Hiroaki NISHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic},
year={2006},
volume={E89-C},
number={11},
pages={1620-1628},
abstract={A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.},
keywords={},
doi={10.1093/ietele/e89-c.11.1620},
ISSN={1745-1353},
month={November},}

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TY - JOUR
TI - Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic
T2 - IEICE TRANSACTIONS on Electronics
SP - 1620
EP - 1628
AU - Michitaka OKUNO
AU - Shinji NISHIMURA
AU - Shin-ichi ISHIDA
AU - Hiroaki NISHI
PY - 2006
DO - 10.1093/ietele/e89-c.11.1620
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2006
AB - A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.
ER -