In most cases, the programmability of Software Defined Network (SDN) refers to the flexibility existing in northbound interface that enables network managers to control the behaviors of the networks. However, the lack of flexibility in data plane conversely results in wasting potentially usable information for controlling flows, especially from network services and applications point of view. For example, OpenFlow switches only deal with L2-L4 headers and ignore the other parts of packet. We propose Ouroboros as a programmable switch logic to increase the flexibility of SDN southbound interface. Ouroboros switches not only remove the limitation of regular OpenFlow switches using packet headers as the reference for packet switching, but also provides a highly flexible interface for network managers to conduct application-specific flow control according to packet content at any arbitrary offsets. Ouroboros can penetrate deeply into packet (e.g., RTP or SIP) protocol headers, or further into packet payload, to process user-defined switching protocol. Our evaluations of Ouroboros on 10Gbps traffic indicates the effectiveness of proposed method.

This letter proposes a new Hybrid Software Defined Network (HSDN) platform for the interoperation with legacy routing protocol to support hardware level network virtualization for multi-tenant environment. By considering current SDN issues in the production network, the proposed platform contributes to solve these issues at reasonable overhead. Our testbed shows that failure convergence time with the proposed platform is almost same as legacy routing protocol. On the other hand, it also shows that hardware level virtualization is supported with stable ICMP response times.

Internet routers need to classify incoming packets quickly into flows in order to support features such as Internet security, virtual private networks and Quality of Service (QoS). Packet classification uses information contained in the packet header, and a predefined rule table in the routers. Packet classification of multiple fields is generally a difficult problem. Hence, researchers have proposed various algorithms. This study proposes a multi-dimensional encoding method in which parameters such as the source IP address, destination IP address, source port, destination port and protocol type are placed in a multi-dimensional space. Similar to the previously best known algorithm, i.e., bitmap intersection, multi-dimensional encoding is based on the multi-dimensional range lookup approach, in which rules are divided into several multi-dimensional collision-free rule sets. These sets are then used to form the new coding vector to replace the bit vector of the bitmap intersection algorithm. The average memory storage of this encoding is θ (LNlog N) for each dimension, where L denotes the number of collision-free rule sets, and N represents the number of rules. The multi-dimensional encoding practically requires much less memory than bitmap intersection algorithm. Additionally, the computation needed for this encoding is as simple as bitmap intersection algorithm. The low memory requirement of the proposed scheme means that it not only decreases the cost of packet classification engine, but also increases the classification performance, since memory represents the performance bottleneck in the packet classification engine implementation using a network processor.

A novel cache-based network processor (NP) architecture that can catch up with next generation 100-Gbps packet-processing throughput by exploiting a nature of network traffic is proposed, and the prototype is evaluated with real network traffic traces. This architecture consists of several small processing units (PUs) and a bit-stream manipulation hardware called a burst-stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC) and a cache-miss handler (CMH). The PLC memorizes a packet-processing method with all table-lookup results, and applies it to subsequent packets that have the same information in their header. To avoid packet-processing blocking, the CMH handles cache-miss packets while registration processing is performed at the PLC. The combination of the PLC and CMH enables most packets to skip the execution at the PUs, which dissipate huge power in conventional NPs. We evaluated an FPGA-based prototype with real core network traffic traces of a WIDE backbone router. From the experimental results, we observed a special case where the packet of minimum size appeared in large quantities, and the cache-based NP was able to achieve 100% throughput with only the 10%-throughput PUs due to the existence of very high temporal locality of network traffic. From the whole results, the cache-based NP would be able to achieve 100-Gbps throughput by using 10- to 40-Gbps throughput PUs. The power consumption of the cache-based NP, which consists of 40-Gbps throughput PUs, is estimated to be only 44.7% that of a conventional NP.

Because of the development of recent broadband access technologies, fair service among users is becoming more important goal. The most promising router mechanisms for providing fair service is per-flow traffic management. However, it is difficult to implement in high-speed core routers because per-flow state management is prohibitively expensive; thus, a large number of flows are aggregated into a small number of queues. This is not an acceptable situation because fairness degrades as the number of flows so aggregated increases. In this paper, we propose a new traffic management scheme called Hierarchically Aggregated Fair Queueing (HAFQ) to provide per-flow fair service. Our scheme can adjust flow aggregation levels according to the queue handling capability of various routers. This means the proposed scheme scales well in high-speed networks. HAFQ improves the fairness among aggregated flows by estimating the number of flows aggregated in a queue and allocating bandwidth to the queue proportionally. In addition, since HAFQ can identify flows having higher arrival rates simultaneously while estimating the number of flows, it enhances the fairness by preferentially dropping their packets. We show that our scheme can provide per-flow fair service through extensive simulation and experiments using a network processor. Since the currently available network processors (Intel IXP1200 in our case) are not high capacity, we also give extensive discussions on the applicability of our scheme to the high-speed core routers.

Faults in computer systems can occur due to a variety of reasons. These include internal effects such as coupling and external effects such as alpha particles. As we move towards smaller manufacturing technologies, the probability of errors for a single transistor is likely to increase. Even if this probability remains the same, the probability of a fault in a processor will increase linearly with the boost in the number of transistors per chip. In many systems, an error has a binary effect, i.e., the output is either correct or erroneous. However, networking systems exhibit different properties. For example, although a portion of the code behaves incorrectly due to a fault, the application can still work correctly. Therefore, measuring the effects of faults on the network processor applications require new measurement metrics to be developed. Particularly, hardware faults need to be measured in the context of their effect on the application behavior. In this paper, we highlight essential application properties and data structures that can be used to measure the error behavior of network processors. Using these metrics, we study the error behavior of seven representative networking applications under different cache access fault probabilities. With this study, we hope to bridge the gap between the circuit-level phenomena and their impact on the application behavior.

A novel cache-based packet-processing-engine (PPE) architecture that achieves low-power consumption and high packet-processing throughput by exploiting the nature of network traffic is proposed. This architecture consists of a processing-unit array and a bit-stream manipulation path called a burst stream path (BSP) that has a special cache mechanism called a process-learning cache (PLC). Network packets, which have the same information in their header, appear repeatedly over a short time. By exploiting that nature, the PLC memorizes the packet-processing method with all results (i. e. , table lookups), and applies it to other packets. The PLC enables most packets to skip the execution at the processing-unit array, which consumes high power. As a practical implementation of the cache-based PPE architecture, P-Gear was designed. In particular, P-Gear was compared with a conventional PPE in terms of silicon die size and power consumption. According to this comparison, in the case of current 0.13-µm CMOS process technology, P-Gear can achieve 100-Gbps (gigabit per second) packet-processing throughput with only 36.5% of the die size and 32.8% of the power consumption required by the conventional PPE. Configurations of both architectures for the 1- to 100-Gbps throughput range were also analyzed. In the throughput range of 10-Gbps or more, P-Gear can achieve the target throughput in a smaller die size than the conventional PPE. And for the whole throughput range, P-Gear can achieve a target throughput at lower power than the conventional PPE.