IEICE TRANSACTIONS on Electronics
VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation
Summary :
An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.02
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.230-242
- Publication Date
- 2006/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.3.230
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
- Category
- System LSIs and Microprocessors
Authors
Noriyuki MINEGISHI
Junichi MIYAKOSHI
Yuki KURODA
Tadayoshi KATAGIRI
Yuki FUKUYAMA
Ryo YAMAMOTO
Masayuki MIYAMA
Kousuke IMAMURA
Hideo HASHIMOTO
Masahiko YOSHIMOTO
Keyword
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Noriyuki MINEGISHI, Junichi MIYAKOSHI, Yuki KURODA, Tadayoshi KATAGIRI, Yuki FUKUYAMA, Ryo YAMAMOTO, Masayuki MIYAMA, Kousuke IMAMURA, Hideo HASHIMOTO, Masahiko YOSHIMOTO, "VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 3, pp. 230-242, March 2006, doi: 10.1093/ietele/e89-c.3.230.
Abstract: An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.02
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.230/_p
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@ARTICLE{e89-c_3_230,
author={Noriyuki MINEGISHI, Junichi MIYAKOSHI, Yuki KURODA, Tadayoshi KATAGIRI, Yuki FUKUYAMA, Ryo YAMAMOTO, Masayuki MIYAMA, Kousuke IMAMURA, Hideo HASHIMOTO, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation},
year={2006},
volume={E89-C},
number={3},
pages={230-242},
abstract={An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.02
keywords={},
doi={10.1093/ietele/e89-c.3.230},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - VLSI Architecture Study of a Real-Time Scalable Optical Flow Processor for Video Segmentation
T2 - IEICE TRANSACTIONS on Electronics
SP - 230
EP - 242
AU - Noriyuki MINEGISHI
AU - Junichi MIYAKOSHI
AU - Yuki KURODA
AU - Tadayoshi KATAGIRI
AU - Yuki FUKUYAMA
AU - Ryo YAMAMOTO
AU - Masayuki MIYAMA
AU - Kousuke IMAMURA
AU - Hideo HASHIMOTO
AU - Masahiko YOSHIMOTO
PY - 2006
DO - 10.1093/ietele/e89-c.3.230
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - An optical flow processor architecture is proposed. It offers accuracy and image-size scalability for video segmentation extraction. The Hierarchical Optical flow Estimation (HOE) algorithm [1] is optimized to provide an appropriate bit-length and iteration number to realize VLSI. The proposed processor architecture provides the following features. First, an algorithm-oriented data-path is introduced to execute all necessary processes of optical flow derivation allowing hardware cost minimization. The data-path is designed using 4-SIMD architecture, which enables high-throughput operation. Thereby, it achieves real-time optical flow derivation with 100% pixel density. Second, it has scalable architecture for higher accuracy and higher resolution. A third feature is the CMOS-process compatible on-chip 2-port DRAM for die-area reduction. The proposed processor has performance for CIF 30 fr/s with 189 MHz clock frequency. Its estimated core size is 6.02
ER -
English
