IEICE TRANSACTIONS on Electronics
Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect
Summary :
In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.327-333
- Publication Date
- 2006/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.3.327
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
- Category
- Interface and Interconnect Techniques
Authors
Keyword
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Yoichi YUYAMA, Akira TSUCHIYA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, "Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 3, pp. 327-333, March 2006, doi: 10.1093/ietele/e89-c.3.327.
Abstract: In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.327/_p
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@ARTICLE{e89-c_3_327,
author={Yoichi YUYAMA, Akira TSUCHIYA, Kazutoshi KOBAYASHI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect},
year={2006},
volume={E89-C},
number={3},
pages={327-333},
abstract={In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.},
keywords={},
doi={10.1093/ietele/e89-c.3.327},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect
T2 - IEICE TRANSACTIONS on Electronics
SP - 327
EP - 333
AU - Yoichi YUYAMA
AU - Akira TSUCHIYA
AU - Kazutoshi KOBAYASHI
AU - Hidetoshi ONODERA
PY - 2006
DO - 10.1093/ietele/e89-c.3.327
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - In this paper, we propose alternate self shielding to remove critical transitions of on-chip global interconnect. Our proposed method alternates shield and signal wires cycle by cycle. The conventional self-shielding methods need additional wires to remove critical transition by encoding. The proposed alternate self-shielding, however, requires no additional wires. We evaluate our method by simulating signal transimission with a circuit simulator. As a result, our proposed method is superior in bit rate compared to others from 10% to 75%.
ER -
English
