IEICE TRANSACTIONS on Electronics
A Statistical Quality Model for Delay Testing
Summary :
In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.349-355
- Publication Date
- 2006/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.3.349
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
- Category
- Signal Integrity and Variability
Authors
Keyword
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Yasuo SATO, Shuji HAMADA, Toshiyuki MAEDA, Atsuo TAKATORI, Seiji KAJIHARA, "A Statistical Quality Model for Delay Testing" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 3, pp. 349-355, March 2006, doi: 10.1093/ietele/e89-c.3.349.
Abstract: In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.349/_p
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@ARTICLE{e89-c_3_349,
author={Yasuo SATO, Shuji HAMADA, Toshiyuki MAEDA, Atsuo TAKATORI, Seiji KAJIHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Statistical Quality Model for Delay Testing},
year={2006},
volume={E89-C},
number={3},
pages={349-355},
abstract={In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.},
keywords={},
doi={10.1093/ietele/e89-c.3.349},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - A Statistical Quality Model for Delay Testing
T2 - IEICE TRANSACTIONS on Electronics
SP - 349
EP - 355
AU - Yasuo SATO
AU - Shuji HAMADA
AU - Toshiyuki MAEDA
AU - Atsuo TAKATORI
AU - Seiji KAJIHARA
PY - 2006
DO - 10.1093/ietele/e89-c.3.349
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - In this paper we introduce a statistical quality model for delay testing that reflects fabrication process quality, design delay margin, and test timing accuracy. The model provides a measure that predicts the chip defect level that cause delay failure, including marginal small delay. We can therefore use the model to make test vectors that are effective in terms of both testing cost and chip quality. The results of experiments using ISCAS89 benchmark data and some large industrial design data reflect various characteristics of our statistical delay quality model.
ER -
English
