IEICE TRANSACTIONS on Electronics
Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond
Summary :
This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.3 pp.384-391
- Publication Date
- 2006/03/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.3.384
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design Technology in the Sub-100 nm Era)
- Category
- Soft Error
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Yoshihide KOMATSU, Yukio ARIMA, Koichiro ISHIBASHI, "Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 3, pp. 384-391, March 2006, doi: 10.1093/ietele/e89-c.3.384.
Abstract: This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.3.384/_p
Copy
@ARTICLE{e89-c_3_384,
author={Yoshihide KOMATSU, Yukio ARIMA, Koichiro ISHIBASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond},
year={2006},
volume={E89-C},
number={3},
pages={384-391},
abstract={This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.},
keywords={},
doi={10.1093/ietele/e89-c.3.384},
ISSN={1745-1353},
month={March},}
Copy
TY - JOUR
TI - Soft Error Hardened Latch Scheme with Forward Body Bias in a 90-nm Technology and Beyond
T2 - IEICE TRANSACTIONS on Electronics
SP - 384
EP - 391
AU - Yoshihide KOMATSU
AU - Yukio ARIMA
AU - Koichiro ISHIBASHI
PY - 2006
DO - 10.1093/ietele/e89-c.3.384
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2006
AB - This paper describes a soft error hardened latch (SEH-Latch) scheme that has an error correction function in the fine process. The storage node of the latch is separated into three electrodes and a soft error on one node is collected by the other two nodes despite the large amount and long-lasting influx of radiation-induced charges. To achieve this, we designed two types of SEH-Latch circuits and a standard latch circuit using 130-nm 2-well, 3-well, and also 90-nm 2-well CMOS processes. The proposed circuit demonstrated immunity that was two orders higher through an irradiation test using alpha-particles, and immunity that was one order higher through neutron irradiation. We also demonstrated forward body bias control, which improves alpha-ray immunity by 26% for a standard latch and achieves 44 times improvement in the proposed latch.
ER -
English
