IEICE TRANSACTIONS on Electronics
The Design of a Monolithic MSTP ASIC
Summary :
A highly integrated monolithic Multi-Service Transport Platform (MSTP) ASIC MSEOSX8-6 incorporating more than 26M transistors has been fabricated with 0.18 µm CMOS technology. The chip is a powerful monolithic MSTP ASIC that supports RPR applications and serves as a generic building block for MSTP network. To accelerate the chip design, we devise a novel methodology called Embedded Reduced Self-Tester (ERST), which integrates the reduced self-tester structure into the chip to shorten the duration of dynamic simulation. Moreover, we divide the design into 12 smaller Hierarchical Layout Blocks (HLB) to enable parallel layout. Resultantly, the whole design has been completed in 5 months, which saves at least 80% of the design cycle in all.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E89-C No.8 pp.1248-1254
- Publication Date
- 2006/08/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e89-c.8.1248
- Type of Manuscript
- PAPER
- Category
- Integrated Electronics
Authors
Keyword
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Peng WANG, Chao ZHANG, Nan HUA, De-peng JIN, Lie-guang ZENG, "The Design of a Monolithic MSTP ASIC" in IEICE TRANSACTIONS on Electronics,
vol. E89-C, no. 8, pp. 1248-1254, August 2006, doi: 10.1093/ietele/e89-c.8.1248.
Abstract: A highly integrated monolithic Multi-Service Transport Platform (MSTP) ASIC MSEOSX8-6 incorporating more than 26M transistors has been fabricated with 0.18 µm CMOS technology. The chip is a powerful monolithic MSTP ASIC that supports RPR applications and serves as a generic building block for MSTP network. To accelerate the chip design, we devise a novel methodology called Embedded Reduced Self-Tester (ERST), which integrates the reduced self-tester structure into the chip to shorten the duration of dynamic simulation. Moreover, we divide the design into 12 smaller Hierarchical Layout Blocks (HLB) to enable parallel layout. Resultantly, the whole design has been completed in 5 months, which saves at least 80% of the design cycle in all.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e89-c.8.1248/_p
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@ARTICLE{e89-c_8_1248,
author={Peng WANG, Chao ZHANG, Nan HUA, De-peng JIN, Lie-guang ZENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={The Design of a Monolithic MSTP ASIC},
year={2006},
volume={E89-C},
number={8},
pages={1248-1254},
abstract={A highly integrated monolithic Multi-Service Transport Platform (MSTP) ASIC MSEOSX8-6 incorporating more than 26M transistors has been fabricated with 0.18 µm CMOS technology. The chip is a powerful monolithic MSTP ASIC that supports RPR applications and serves as a generic building block for MSTP network. To accelerate the chip design, we devise a novel methodology called Embedded Reduced Self-Tester (ERST), which integrates the reduced self-tester structure into the chip to shorten the duration of dynamic simulation. Moreover, we divide the design into 12 smaller Hierarchical Layout Blocks (HLB) to enable parallel layout. Resultantly, the whole design has been completed in 5 months, which saves at least 80% of the design cycle in all.},
keywords={},
doi={10.1093/ietele/e89-c.8.1248},
ISSN={1745-1353},
month={August},}
Copy
TY - JOUR
TI - The Design of a Monolithic MSTP ASIC
T2 - IEICE TRANSACTIONS on Electronics
SP - 1248
EP - 1254
AU - Peng WANG
AU - Chao ZHANG
AU - Nan HUA
AU - De-peng JIN
AU - Lie-guang ZENG
PY - 2006
DO - 10.1093/ietele/e89-c.8.1248
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E89-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2006
AB - A highly integrated monolithic Multi-Service Transport Platform (MSTP) ASIC MSEOSX8-6 incorporating more than 26M transistors has been fabricated with 0.18 µm CMOS technology. The chip is a powerful monolithic MSTP ASIC that supports RPR applications and serves as a generic building block for MSTP network. To accelerate the chip design, we devise a novel methodology called Embedded Reduced Self-Tester (ERST), which integrates the reduced self-tester structure into the chip to shorten the duration of dynamic simulation. Moreover, we divide the design into 12 smaller Hierarchical Layout Blocks (HLB) to enable parallel layout. Resultantly, the whole design has been completed in 5 months, which saves at least 80% of the design cycle in all.
ER -
English
