CMOS Imaging Devices for New Markets of Vision Systems

Shoji KAWAHITO

doi:10.1093/ietele/e90-c.10.1858

CMOS Imaging Devices for New Markets of Vision Systems

Shoji KAWAHITO

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This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.

Publication: IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.1858-1868

Publication Date: 2007/10/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e90-c.10.1858

Type of Manuscript: Special Section INVITED PAPER (Special Section on VLSI Technology toward Frontiers of New Market)

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Shoji KAWAHITO, "CMOS Imaging Devices for New Markets of Vision Systems" in IEICE TRANSACTIONS on Electronics, vol. E90-C, no. 10, pp. 1858-1868, October 2007, doi: 10.1093/ietele/e90-c.10.1858.
Abstract: This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.10.1858/_p

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@ARTICLE{e90-c_10_1858,
author={Shoji KAWAHITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Imaging Devices for New Markets of Vision Systems},
year={2007},
volume={E90-C},
number={10},
pages={1858-1868},
abstract={This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.},
keywords={},
doi={10.1093/ietele/e90-c.10.1858},
ISSN={1745-1353},
month={October},}

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TY - JOUR
TI - CMOS Imaging Devices for New Markets of Vision Systems
T2 - IEICE TRANSACTIONS on Electronics
SP - 1858
EP - 1868
AU - Shoji KAWAHITO
PY - 2007
DO - 10.1093/ietele/e90-c.10.1858
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2007
AB - This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.
ER -