This paper presents a multi-channel biomedical sensor system with system-level chopping and stochastic analog-to-digital (A/D) conversion techniques. The system-level chopping technique extends the input-signal bandwidth and reduces the interchannel crosstalk caused by multiplexing. The system-level chopping can replace an analog low-pass filter (LPF) with a digital filter and can reduce its area occupation. The stochastic A/D conversion technique realizes power-efficient resolution enhancement. A novel auto-calibration technique is also proposed for the stochastic A/D conversion technique. The proposed system includes a prototype analog front-end (AFE) IC fabricated using a 130 nm CMOS process. The fabricated AFE IC improved its interchannel crosstalk by 40 dB compared with the conventional analog chopping architecture. The AFE IC achieved SNDR of 62.9 dB at a sampling rate of 31.25 kSps while consuming 9.6 μW from a 1.2 V power supply. The proposed resolution enhancement technique improved the measured SNDR by 4.5 dB.

This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.

In the present paper, we propose a novel high-resolution analog-to-digital converter (ADC) for low-power biomedical analog front-ends, which we call the successive stochastic approximation ADC. The proposed ADC uses a stochastic flash ADC (SF-ADC) to realize a digitally controlled variable-threshold comparator in a successive-approximation-register ADC (SAR-ADC), which can correct errors originating from the internal digital-to-analog converter in the SAR-ADC. For the residual error after SAR-ADC operation, which can be smaller than thermal noise, the SF-ADC uses the statistical characteristics of noise to achieve high resolution. The SF-ADC output for the residual signal is combined with the SAR-ADC output to obtain high-precision output data using the supervised machine learning method.

This letter presents a new time-digital single-slope ADC (TDSS) architecture for CMOS image sensors. In the proposed ADC, a conventional single-slope ADC is used in coarse phase and a time to digital convertor is employed in fine phase. Through second comparison of the two different slope voltages (discharge input voltage and ramp voltage), the proposed ADC achieves low bit precision compensation. Compared with multiple-ramp single-slope (MRSS) ADC, the proposed ADC not only has a simple digital judgment circuit, but also increases conversion speed without complicated structure of ramp generator. A 10-bit TDSS ADC consisting of 7-bit conventional single-slope ADC and 3-bit time to digital converter was realized in a 0.13µm CIS process. Simulations demonstrate that the conversion speed of a TDSS ADC is almost 3.5 times faster than that of a single-slope ADC.

This paper discusses recent trends in the area of low-power, high-performance A/D conversion. We examine survey data collected over the past twelve years to show that the conversion energy of ADCs has halved every two years, while the speed-resolution product has doubled approximately only every four years. A closer inspection on the impact of technology scaling, and developments in ADC design are then presented to explain the observed trends. Finally, we review opportunities in digitally assisted design for the most popular converter architectures.

This paper proposes a 12-bit 3.7-MS/s pipelined A/D Converter based on the novel capacitor mismatch calibration technique. The conventional stage is improved to an algorithmic circuit involving charge summing, capacitors' exchange and charge redistribution, simply through introducing some extra switches into the analog circuit. This proposed ADC obtains the linearity beyond the accuracy of the capacitor match and verifies the validity of reducing the nonlinear error from the capacitor mismatch to the second order without additional power dissipation through the novel capacitor mismatch calibration technique. It is processed in 0.5 µm CMOS technology. The transistor-level simulation results show that 72.6 dB SNDR, 78.5 dB SFDR are obtained for a 2 V Vpp 159.144 kHz sine input sampled at 3.7 MS/s. The whole power dissipation of this ADC is 33.4 mW at the power supply of 5 V.

This paper reviews and discusses devices, circuits, and signal processing techniques for CMOS imaging SoC's based on column-parallel processing architecture. The pinned photodiode technology improves the noise characteristics at the device level to be comparable to CCD image sensors and as a result, low-noise design in CMOS image sensors has been shifted to the reduction of noise at the circuit level. Techniques for reducing the circuit noise are discussed. The performance of the imaging SoC's greatly depends on that of the analog-to-digital converter (ADC) used at the column. Three possible architectures of the column-parallel ADC are reviewed and their advantage and disadvantage are discussed. Finally, a few applications of the device and circuit techniques and the column-parallel processing architecture are described.

Performance analysis of ultra-fast all-optical analog-to-digital converter using optical multiple-level thresholding module based on self-frequency shift in fiber is described. In analog-to-digital conversion, the purposes of optical sampling and optical quantization are in the possibility of the speed-up of sampling and quantization processes using various ultra-fast nonlinear phenomena depending on an intensity of a light. The result of analysis indicates that the number of achievable quantized levels of the proposed approach is in the increasing tendency with an increase in the peak power of an input pulse.

This paper proposes a 15-bit 10-MS/s pipelined ADC based on the incomplete settling principle. The traditional complete settling stage is improved to the incomplete settling structure through dividing the sampling clock of the traditional stage into two parts for discharging the sampling and feedback capacitors and completing the sampling, respectively. The proposed ADC verifies the correction and validity of optimizing ADCs' conversion speed without additional power consumption through the incomplete settling. This ADC employs scaling-down scheme to achieve low power dissipation and utilizes full-differential structure, bottom-plate-sampling, and capacitor-sharing techniques as well as bit-by-bit digital self-calibration to increase the ADC's linearity. It is processed in 0.18 µm 1P6M CMOS mixed-mode technology. Simulation results show that 82 dB SNDR and 87 dB SFDR are obtained at the sampling rate of 10 MHz with the input sine frequency of 100 kHz and the whole static power dissipation is 21.94 mW.

This paper describes an adaptive fingerprint-sensing scheme for a user authentication system with a fingerprint sensor LSI to obtain high-quality fingerprint images suitable for identification. The scheme is based on novel evaluation indexes of fingerprint-image quality and adjustable analog-to-digital (A/D) conversion. The scheme adjusts dynamically an A/D conversion range of the fingerprint sensor LSI while evaluating the image quality during real-time fingerprint-sensing operation. The evaluation indexes pertain to the contrast and the ridgelines of a fingerprint image. The A/D conversion range is adjusted by changing quantization resolution and offset. We developed a fingerprint sensor LSI and a user authentication system to evaluate the adaptive fingerprint-sensing scheme. The scheme obtained a fingerprint image suitable for identification and the system achieved an accurate identification rate with 0.36% of the false rejection rate (FRR) at 0.075% of the false acceptance rate (FAR). This confirms that the scheme is very effective in achieving accurate identification.