IEICE TRANSACTIONS on Fundamentals
Two-Step Column-Parallel SAR/Single-Slope ADC for CMOS Image Sensors
Summary :
This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E101-A No.2 pp.434-437
- Publication Date
- 2018/02/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E101.A.434
- Type of Manuscript
- Special Section LETTER (Special Section on Analog Circuit Techniques and Related Topics)
- Category
Authors
Hejiu ZHANG
Xi'an University of Technology
Ningmei YU
Xi'an University of Technology
Nan LYU
Xi'an University of Technology
Keren LI
Xi'an University of Technology
Keyword
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Hejiu ZHANG, Ningmei YU, Nan LYU, Keren LI, "Two-Step Column-Parallel SAR/Single-Slope ADC for CMOS Image Sensors" in IEICE TRANSACTIONS on Fundamentals,
vol. E101-A, no. 2, pp. 434-437, February 2018, doi: 10.1587/transfun.E101.A.434.
Abstract: This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E101.A.434/_p
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@ARTICLE{e101-a_2_434,
author={Hejiu ZHANG, Ningmei YU, Nan LYU, Keren LI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Two-Step Column-Parallel SAR/Single-Slope ADC for CMOS Image Sensors},
year={2018},
volume={E101-A},
number={2},
pages={434-437},
abstract={This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.},
keywords={},
doi={10.1587/transfun.E101.A.434},
ISSN={1745-1337},
month={February},}
Copy
TY - JOUR
TI - Two-Step Column-Parallel SAR/Single-Slope ADC for CMOS Image Sensors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 434
EP - 437
AU - Hejiu ZHANG
AU - Ningmei YU
AU - Nan LYU
AU - Keren LI
PY - 2018
DO - 10.1587/transfun.E101.A.434
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E101-A
IS - 2
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - February 2018
AB - This letter presents a 12-bit column-parallel hybrid two-step successive approximation register/single-slope analog-to-digital converter (SAR/SS ADC) for CMOS image sensor (CIS). For achieving a high conversion speed, a simple SAR ADC is used in upper 6-bit conversion and a conventional SS ADC is used in lower 6-bit conversion. To reduce the power consumption, a comparator is shared in each column, and a 6-bit ramp generator is shared by all columns. This ADC is designed in SMIC 0.18µm CMOS process. At a clock frequency of 22.7MHz, the conversion time is 3.2µs. The ADC has a DNL of -0.31/+0.38LSB and an INL of -0.86/+0.8LSB. The power consumption of each column ADC is 89µW and the ramp generator is 763µW.
ER -
English
