IEICE TRANSACTIONS on Electronics
A 90 nm 48
48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations
Summary :
We have fabricated a LUT-based FPGA device with functionalities measuring within-die variations in a 90 nm process. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Random variations are dominant in a 48
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.1919-1926
- Publication Date
- 2007/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.10.1919
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
- Category
- Low-Power and High-Performance VLSI Circuit Technology
Authors
Keyword
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Kazutoshi KOBAYASHI, Kazuya KATSUKI, Manabu KOTANI, Yuuri SUGIHARA, Yohei KUME, Hidetoshi ONODERA, "A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 10, pp. 1919-1926, October 2007, doi: 10.1093/ietele/e90-c.10.1919.
Abstract: We have fabricated a LUT-based FPGA device with functionalities measuring within-die variations in a 90 nm process. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Random variations are dominant in a 48
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.10.1919/_p
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@ARTICLE{e90-c_10_1919,
author={Kazutoshi KOBAYASHI, Kazuya KATSUKI, Manabu KOTANI, Yuuri SUGIHARA, Yohei KUME, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations},
year={2007},
volume={E90-C},
number={10},
pages={1919-1926},
abstract={We have fabricated a LUT-based FPGA device with functionalities measuring within-die variations in a 90 nm process. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Random variations are dominant in a 48
keywords={},
doi={10.1093/ietele/e90-c.10.1919},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - A 90 nm 4848 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations
T2 - IEICE TRANSACTIONS on Electronics
SP - 1919
EP - 1926
AU - Kazutoshi KOBAYASHI
AU - Kazuya KATSUKI
AU - Manabu KOTANI
AU - Yuuri SUGIHARA
AU - Yohei KUME
AU - Hidetoshi ONODERA
PY - 2007
DO - 10.1093/ietele/e90-c.10.1919
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2007
AB - We have fabricated a LUT-based FPGA device with functionalities measuring within-die variations in a 90 nm process. Variations are measured using ring oscillators implemented as a configuration of the FPGA. Random variations are dominant in a 48
ER -
English
