IEICE TRANSACTIONS on Electronics
Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes
Summary :
This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.10 pp.1949-1956
- Publication Date
- 2007/10/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.10.1949
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Technology toward Frontiers of New Market)
- Category
- Next-Generation Memory for SoC
Authors
Yasuhiro MORITA
Hidehiro FUJIWARA
Hiroki NOGUCHI
Yusuke IGUCHI
Koji NII
Hiroshi KAWAGUCHI
Masahiko YOSHIMOTO
Keyword
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Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Yusuke IGUCHI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 10, pp. 1949-1956, October 2007, doi: 10.1093/ietele/e90-c.10.1949.
Abstract: This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.10.1949/_p
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@ARTICLE{e90-c_10_1949,
author={Yasuhiro MORITA, Hidehiro FUJIWARA, Hiroki NOGUCHI, Yusuke IGUCHI, Koji NII, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes},
year={2007},
volume={E90-C},
number={10},
pages={1949-1956},
abstract={This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.},
keywords={},
doi={10.1093/ietele/e90-c.10.1949},
ISSN={1745-1353},
month={October},}
Copy
TY - JOUR
TI - Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes
T2 - IEICE TRANSACTIONS on Electronics
SP - 1949
EP - 1956
AU - Yasuhiro MORITA
AU - Hidehiro FUJIWARA
AU - Hiroki NOGUCHI
AU - Yusuke IGUCHI
AU - Koji NII
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2007
DO - 10.1093/ietele/e90-c.10.1949
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2007
AB - This paper shows that an 8T SRAM cell is superior to a 6T cell in terms of cell area in a future process. At a 65-nm node and later, the 6T cell comprised of the minimum-channel-length transistors cannot make the minimum area because of threshold-voltage variation. In contrast, the 8T cell can employ the optimized transistors and achieves the minimum area even if it is used as a single-port SRAM. In a 32-nm process, the 8T-cell area is smaller than the 6T cell by 14.6% at a supply voltage of 0.8 V. We also discuss the area and access time comparisons between the 6T-SRAM and 8T-SRAM macros.
ER -
English
