Cooperative Cache System: A Low Power Cache System for Embedded Processors
Summary :
This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 µm 4-metal process technology.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E90-C No.4 pp.708-717
- Publication Date
- 2007/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e90-c.4.708
- Type of Manuscript
- Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
- Category
- Digital
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Gi-Ho PARK, Kil-Whan LEE, Tack-Don HAN, Shin-Dug KIM, "Cooperative Cache System: A Low Power Cache System for Embedded Processors" in IEICE TRANSACTIONS on Electronics,
vol. E90-C, no. 4, pp. 708-717, April 2007, doi: 10.1093/ietele/e90-c.4.708.
Abstract: This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 µm 4-metal process technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e90-c.4.708/_p
Copy
@ARTICLE{e90-c_4_708,
author={Gi-Ho PARK, Kil-Whan LEE, Tack-Don HAN, Shin-Dug KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Cooperative Cache System: A Low Power Cache System for Embedded Processors},
year={2007},
volume={E90-C},
number={4},
pages={708-717},
abstract={This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 µm 4-metal process technology.},
keywords={},
doi={10.1093/ietele/e90-c.4.708},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Cooperative Cache System: A Low Power Cache System for Embedded Processors
T2 - IEICE TRANSACTIONS on Electronics
SP - 708
EP - 717
AU - Gi-Ho PARK
AU - Kil-Whan LEE
AU - Tack-Don HAN
AU - Shin-Dug KIM
PY - 2007
DO - 10.1093/ietele/e90-c.4.708
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E90-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2007
AB - This paper presents a dual data cache system structure, called a cooperative cache system, that is designed as a low power cache structure for embedded processors. The cooperative cache system consists of two caches, i.e., a direct-mapped temporal oriented cache (TOC) and a four-way set-associative spatial oriented cache (SOC). The cooperative cache system achieves improvement in performance and reduction in power consumption by virtue of the structural characteristics of the two caches designed inherently to help each other. An evaluation chip of an embedded processor having the cooperative cache system is manufactured by Samsung Electronics Co. with 0.25 µm 4-metal process technology.
ER -
English
