6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator

Yun-Jeong KIM; Jong-Ho LEE; Ja-Hyun KOO; Kwang-Hyun BAEK; Suki KIM

doi:10.1093/ietele/e91-c.3.392

6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator

Yun-Jeong KIM, Jong-Ho LEE, Ja-Hyun KOO, Kwang-Hyun BAEK, Suki KIM

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In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220 MHz at 1.6 GS/s, and almost five effective bits for 660 MHz input at 1.6 GS/s. Peak INL and DNL are less than 0.5 LSB and 0.45 LSB, respectively. This ADC consumes 85 mW from 1.8 V at 1.6 GS/s and occupies an active area of 0.27 mm². It is fabricated in 0.18-µm CMOS.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.3 pp.392-395

Publication Date: 2008/03/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.3.392

Type of Manuscript: LETTER

Category: Electronic Circuits

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Yun-Jeong KIM, Jong-Ho LEE, Ja-Hyun KOO, Kwang-Hyun BAEK, Suki KIM, "6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 3, pp. 392-395, March 2008, doi: 10.1093/ietele/e91-c.3.392.
Abstract: In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220 MHz at 1.6 GS/s, and almost five effective bits for 660 MHz input at 1.6 GS/s. Peak INL and DNL are less than 0.5 LSB and 0.45 LSB, respectively. This ADC consumes 85 mW from 1.8 V at 1.6 GS/s and occupies an active area of 0.27 mm². It is fabricated in 0.18-µm CMOS.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.3.392/_p

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@ARTICLE{e91-c_3_392,
author={Yun-Jeong KIM, Jong-Ho LEE, Ja-Hyun KOO, Kwang-Hyun BAEK, Suki KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator},
year={2008},
volume={E91-C},
number={3},
pages={392-395},
abstract={In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220 MHz at 1.6 GS/s, and almost five effective bits for 660 MHz input at 1.6 GS/s. Peak INL and DNL are less than 0.5 LSB and 0.45 LSB, respectively. This ADC consumes 85 mW from 1.8 V at 1.6 GS/s and occupies an active area of 0.27 mm². It is fabricated in 0.18-µm CMOS.},
keywords={},
doi={10.1093/ietele/e91-c.3.392},
ISSN={1745-1353},
month={March},}

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TY - JOUR
TI - 6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator
T2 - IEICE TRANSACTIONS on Electronics
SP - 392
EP - 395
AU - Yun-Jeong KIM
AU - Jong-Ho LEE
AU - Ja-Hyun KOO
AU - Kwang-Hyun BAEK
AU - Suki KIM
PY - 2008
DO - 10.1093/ietele/e91-c.3.392
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2008
AB - In this paper, we describe a 6-bit 1.6-GS/s flash analog to digital converter (ADC). To reduce the power consumption and active area, we propose a new interpolation architecture using a symmetric three-input comparator. This ADC achieves 5.56 effective bits for input frequencies up to 220 MHz at 1.6 GS/s, and almost five effective bits for 660 MHz input at 1.6 GS/s. Peak INL and DNL are less than 0.5 LSB and 0.45 LSB, respectively. This ADC consumes 85 mW from 1.8 V at 1.6 GS/s and occupies an active area of 0.27 mm². It is fabricated in 0.18-µm CMOS.
ER -