IEICE TRANSACTIONS on Electronics
Power-Aware Compiler Controllable Chip Multiprocessor
Summary :
A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.432-439
- Publication Date
- 2008/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.4.432
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
- Category
Authors
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Hiroaki SHIKANO, Jun SHIRAKO, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA, "Power-Aware Compiler Controllable Chip Multiprocessor" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 4, pp. 432-439, April 2008, doi: 10.1093/ietele/e91-c.4.432.
Abstract: A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.432/_p
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@ARTICLE{e91-c_4_432,
author={Hiroaki SHIKANO, Jun SHIRAKO, Yasutaka WADA, Keiji KIMURA, Hironori KASAHARA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Power-Aware Compiler Controllable Chip Multiprocessor},
year={2008},
volume={E91-C},
number={4},
pages={432-439},
abstract={A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.},
keywords={},
doi={10.1093/ietele/e91-c.4.432},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - Power-Aware Compiler Controllable Chip Multiprocessor
T2 - IEICE TRANSACTIONS on Electronics
SP - 432
EP - 439
AU - Hiroaki SHIKANO
AU - Jun SHIRAKO
AU - Yasutaka WADA
AU - Keiji KIMURA
AU - Hironori KASAHARA
PY - 2008
DO - 10.1093/ietele/e91-c.4.432
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - A power-aware compiler controllable chip multiprocessor (CMP) is presented and its performance and power consumption are evaluated with the optimally scheduled advanced multiprocessor (OSCAR) parallelizing compiler. The CMP is equipped with power control registers that change clock frequency and power supply voltage to functional units including processor cores, memories, and an interconnection network. The OSCAR compiler carries out coarse-grain task parallelization of programs and reduces power consumption using architectural power control support and the compiler's power saving scheme. The performance evaluation shows that MPEG-2 encoding on the proposed CMP with four CPUs results in 82.6% power reduction in real-time execution mode with a deadline constraint on its sequential execution time. Furthermore, MP3 encoding on a heterogeneous CMP with four CPUs and four accelerators results in 53.9% power reduction at 21.1-fold speed-up in performance against its sequential execution in the fastest execution mode.
ER -
English
