IEICE TRANSACTIONS on Electronics
Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation
Summary :
In this paper, a multiple-valued current-mode (MVCM) circuit based on active-load dual-rail differential logic is proposed for a high-performance arithmetic VLSI system with crosstalk-noise immunity. The use of dual-rail complementary differential-pair circuits (DPCs), whose outputs are summed up by wiring makes it possible to reduce the common-mode noise, and yet enhance the switching speed. By using the diode-connected cross-coupled PMOS active loads, the rapid transition of switching in the DPC is relaxed appropriately, which can also eliminate spiked input noise. It is demonstrated that the noise reduction ratio and the switching delay of the proposed MVCM circuit in a 90 nm CMOS technology is superior to those of the corresponding ordinary implementation.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E91-C No.4 pp.589-594
- Publication Date
- 2008/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1093/ietele/e91-c.4.589
- Type of Manuscript
- Special Section PAPER (Special Section on Advanced Technologies in Digital LSIs and Memories)
- Category
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Masatomo MIURA, Takahiro HANYU, "Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 4, pp. 589-594, April 2008, doi: 10.1093/ietele/e91-c.4.589.
Abstract: In this paper, a multiple-valued current-mode (MVCM) circuit based on active-load dual-rail differential logic is proposed for a high-performance arithmetic VLSI system with crosstalk-noise immunity. The use of dual-rail complementary differential-pair circuits (DPCs), whose outputs are summed up by wiring makes it possible to reduce the common-mode noise, and yet enhance the switching speed. By using the diode-connected cross-coupled PMOS active loads, the rapid transition of switching in the DPC is relaxed appropriately, which can also eliminate spiked input noise. It is demonstrated that the noise reduction ratio and the switching delay of the proposed MVCM circuit in a 90 nm CMOS technology is superior to those of the corresponding ordinary implementation.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.4.589/_p
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@ARTICLE{e91-c_4_589,
author={Masatomo MIURA, Takahiro HANYU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation},
year={2008},
volume={E91-C},
number={4},
pages={589-594},
abstract={In this paper, a multiple-valued current-mode (MVCM) circuit based on active-load dual-rail differential logic is proposed for a high-performance arithmetic VLSI system with crosstalk-noise immunity. The use of dual-rail complementary differential-pair circuits (DPCs), whose outputs are summed up by wiring makes it possible to reduce the common-mode noise, and yet enhance the switching speed. By using the diode-connected cross-coupled PMOS active loads, the rapid transition of switching in the DPC is relaxed appropriately, which can also eliminate spiked input noise. It is demonstrated that the noise reduction ratio and the switching delay of the proposed MVCM circuit in a 90 nm CMOS technology is superior to those of the corresponding ordinary implementation.},
keywords={},
doi={10.1093/ietele/e91-c.4.589},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Highly Reliable Multiple-Valued Current-Mode Comparator Based on Active-Load Dual-Rail Operation
T2 - IEICE TRANSACTIONS on Electronics
SP - 589
EP - 594
AU - Masatomo MIURA
AU - Takahiro HANYU
PY - 2008
DO - 10.1093/ietele/e91-c.4.589
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2008
AB - In this paper, a multiple-valued current-mode (MVCM) circuit based on active-load dual-rail differential logic is proposed for a high-performance arithmetic VLSI system with crosstalk-noise immunity. The use of dual-rail complementary differential-pair circuits (DPCs), whose outputs are summed up by wiring makes it possible to reduce the common-mode noise, and yet enhance the switching speed. By using the diode-connected cross-coupled PMOS active loads, the rapid transition of switching in the DPC is relaxed appropriately, which can also eliminate spiked input noise. It is demonstrated that the noise reduction ratio and the switching delay of the proposed MVCM circuit in a 90 nm CMOS technology is superior to those of the corresponding ordinary implementation.
ER -
English
