Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Seongjae CHO; Il Han PARK; Jung Hoon LEE; Jang-Gn YUN; Doo-Hyun KIM; Jong Duk LEE; Hyungcheol SHIN; Byung-Gook PARK

doi:10.1093/ietele/e91-c.5.731

Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)

Seongjae CHO, Il Han PARK, Jung Hoon LEE, Jang-Gn YUN, Doo-Hyun KIM, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK

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Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.

Publication: IEICE TRANSACTIONS on Electronics Vol.E91-C No.5 pp.731-735

Publication Date: 2008/05/01

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Online ISSN: 1745-1353

DOI: 10.1093/ietele/e91-c.5.731

Type of Manuscript: Special Section PAPER (Special Section on Fundamentals and Applications of Advanced Semiconductor Devices)

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Seongjae CHO, Il Han PARK, Jung Hoon LEE, Jang-Gn YUN, Doo-Hyun KIM, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK, "Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)" in IEICE TRANSACTIONS on Electronics, vol. E91-C, no. 5, pp. 731-735, May 2008, doi: 10.1093/ietele/e91-c.5.731.
Abstract: Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.5.731/_p

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@ARTICLE{e91-c_5_731,
author={Seongjae CHO, Il Han PARK, Jung Hoon LEE, Jang-Gn YUN, Doo-Hyun KIM, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK, },
journal={IEICE TRANSACTIONS on Electronics},
title={Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)},
year={2008},
volume={E91-C},
number={5},
pages={731-735},
abstract={Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.},
keywords={},
doi={10.1093/ietele/e91-c.5.731},
ISSN={1745-1353},
month={May},}

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TY - JOUR
TI - Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI)
T2 - IEICE TRANSACTIONS on Electronics
SP - 731
EP - 735
AU - Seongjae CHO
AU - Il Han PARK
AU - Jung Hoon LEE
AU - Jang-Gn YUN
AU - Doo-Hyun KIM
AU - Jong Duk LEE
AU - Hyungcheol SHIN
AU - Byung-Gook PARK
PY - 2008
DO - 10.1093/ietele/e91-c.5.731
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2008
AB - Efforts have been devoted to maximizing memory array densities. However, as the devices are scaled down in dimension and getting closer to each other, electrical interference phenomena among devices become more prominent. Various features of 3-D memory devices are proposed for the enhancement of memory array density. In this study, we mention 3-D NAND flash memory device having pillar structure as the representative, and investigate the paired cell interference (PCI) which inevitably occurs in the read operation for 3-D memory devices in this feature. Furthermore, criteria for setting up the read operation bias schemes are also examined in existence with PCI.
ER -