A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (Vth) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (Vth, DIBL and SS) by considering device structure and doping profile of the cell.
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Han-A-Reum JUNG, Kyoung-Rok HAN, Young-Min KIM, Jong-Ho LEE, "Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 5, pp. 736-741, May 2008, doi: 10.1093/ietele/e91-c.5.736.
Abstract: A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (Vth) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (Vth, DIBL and SS) by considering device structure and doping profile of the cell.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.5.736/_p
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@ARTICLE{e91-c_5_736,
author={Han-A-Reum JUNG, Kyoung-Rok HAN, Young-Min KIM, Jong-Ho LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure},
year={2008},
volume={E91-C},
number={5},
pages={736-741},
abstract={A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (Vth) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (Vth, DIBL and SS) by considering device structure and doping profile of the cell.},
keywords={},
doi={10.1093/ietele/e91-c.5.736},
ISSN={1745-1353},
month={May},}
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TY - JOUR
TI - Device Design of SONOS Flash Memory Cell with Saddle Type Channel Structure
T2 - IEICE TRANSACTIONS on Electronics
SP - 736
EP - 741
AU - Han-A-Reum JUNG
AU - Kyoung-Rok HAN
AU - Young-Min KIM
AU - Jong-Ho LEE
PY - 2008
DO - 10.1093/ietele/e91-c.5.736
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2008
AB - A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (Vth) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (Vth, DIBL and SS) by considering device structure and doping profile of the cell.
ER -