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Hyun Woo KIM Dong Hun KIM Joo Hyung YOU Tae Whan KIM
The programming characteristics of polysilicon-aluminum oxide-nitride-oxide-silicon (SANOS) nonvolatile memory devices with Al2O3 and SiO2 stacked tunneling layers were investigated. The electron and hole drifts in the Si3N4 layer were calculated to determine the program speed of the proposed SANOS devices. Simulation results showed that enhancement of the programming speed in SANOS was achieved by utilizing SiO2 and Al2O3 stacked tunneling layers.
Jae Sub OH Kwang Il CHOI Young Su KIM Min Ho KANG Myeong Ho SONG Sung Kyu LIM Dong Eun YOO Jeong Gyu PARK Hi Deok LEE Ga Won LEE
A HfO2 as the charge-storage layer with the physical thickness thinner than 4 nm in silicon-oxide-high-k oxide-oxide-silicon (SOHOS) flash memory was investigated. Compared to the conventional silicon-oxide-nitride-oxide-silicon (SONOS) flash memory, the SOHOS shows the slow operational speed and exhibits the poorer retention characteristics. These are attributed to the thin physical thickness below 4 nm and the crystallization of the HfO2 to contribute the lateral migration of the trapped charge in the trapping layer during high temperature annealing process.
Doo-Hyun KIM Il Han PARK Seongjae CHO Jong Duk LEE Hyungcheol SHIN Byung-Gook PARK
This paper presents a detailed study of the retention characteristics in scaled multi-bit SONOS flash memories. By calculating the oxide field and tunneling currents, we evaluate the charge trapping mechanism. We calculate transient retention dynamics with the ONO fields, trapped charge, and tunneling currents. All the parameters were obtained by physics-based equations and without any fitting parameters or optimization steps. The results can be used with nanoscale nonvolatile memory. This modeling accounts for the VT shift as a function of trapped charge density, time, silicon fin thickness and type of trapped charge, and can be used for optimizing the ONO geometry and parameters for maximum performance.
Han-A-Reum JUNG Kyoung-Rok HAN Young-Min KIM Jong-Ho LEE
A new SONOS flash memory device with recess channel and side-gate was proposed and designed in terms of recess depth, doping profile, and side-gate length for sub-40 nm flash memory technology. The key features of the devices were characterized through 3-dimensional device simulation. This cell structure can store 2 or more bits of data in a cell when it is applied to NOR flash memory. It was shown that channel doping profile is very important depending on NOR or NAND applications. In NOR flash memory application, the localized channel doping under the source/drain junction is very important in designing threshold voltage (Vth) and suppression of drain induced barrier lowering (DIBL). In our work, this cell structure is studied not only for NAND flash memory application but also for NOR flash application. The device design was performed in terms of electrical characteristics (Vth, DIBL and SS) by considering device structure and doping profile of the cell.
Kuk-Hwan KIM Hyunjin LEE Yang-Kyu CHOI
A 2-bit operational metal/silicon-oxide-nitride-oxide-silicon (MONOS/SONOS) nonvolatile memory using an asymmetric double-gate (ASDG) MOSFET was studied to double flash memory density. The 2-bit programming and erasing was performed by Fowler-Nordheim (FN) tunneling in a NAND array architecture using individually controlled gates. A threshold voltage shift of programmed states for the 2-bit operation was investigated with the aid of a SILVACO® simulator in both sides of the gate by changing gate workfunctions and tunneling oxide thicknesses. In this paper, the scalability of the device down to 30 nm was demonstrated by numerical simulation. Additionally, guidelines of the 2-bit ASDG nonvolatile memory (NVM) structure and operational conditions were proposed for "program," "read," and "erase."