A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family

Yoji NISHIO; Noriaki OKA; Shigeru TAKAHASHI; Manabu SHIBATA

A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family

Yoji NISHIO, Noriaki OKA, Shigeru TAKAHASHI, Manabu SHIBATA

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A mixed BiCMOS/CMOS channelless gate array family with 3-metal-layer wiring using a 5 V version, 0.5 µm BiCMOS technology is discussed. The speed and power performance of CMOS gates are superior to those of BiCMOS gates for light load capacitance. The power-delay product of CMOS gates at light load is 50% less than that of BiCMOS gates. Therefore, by using CMOS and BiCMOS gates selectively according to the weight of the capacitance load, the performance of the BiCMOS gate array is enhanced. Then, a new mixed BiCMOS/CMOS basic cell structure which can be used as BiCMOS or CMOS gates, which go to the wiring channels, was developed. The area efficiency of the developed basic cell is 16% better than that of the conventional basic cell, as got from design automation experience, etc. The wiring method of the power supply reinforcement lines of the third metal layer in a large chip was examined from the viewpoint of the number of useful basic cells. As a result, by locating the reinforcement lines at every basic cell, the number of useful basic cells is about 14% more than that of another method in which the reinforcement lines are located at certain intervals of basic cells. Propagation delay time of the 2-input NAND is 190 ps at fan out 10 load. Under a light load, a pure CMOS NAND is faster, achieving a 140 ps gate delay at fan out 2 load. This gate array family can be applied to high speed processors.

Publication: IEICE TRANSACTIONS on Electronics Vol.E74-C No.11 pp.3749-3756

Publication Date: 1991/11/25

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Type of Manuscript: Special Section PAPER (Special Issue on the High Performance ASIC and Microprocessor)

Category: Circuit Design

Authors

Yoji NISHIO
Noriaki OKA
Shigeru TAKAHASHI
Manabu SHIBATA

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Yoji NISHIO, Noriaki OKA, Shigeru TAKAHASHI, Manabu SHIBATA, "A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family" in IEICE TRANSACTIONS on Electronics, vol. E74-C, no. 11, pp. 3749-3756, November 1991, doi: .
Abstract: A mixed BiCMOS/CMOS channelless gate array family with 3-metal-layer wiring using a 5 V version, 0.5 µm BiCMOS technology is discussed. The speed and power performance of CMOS gates are superior to those of BiCMOS gates for light load capacitance. The power-delay product of CMOS gates at light load is 50% less than that of BiCMOS gates. Therefore, by using CMOS and BiCMOS gates selectively according to the weight of the capacitance load, the performance of the BiCMOS gate array is enhanced. Then, a new mixed BiCMOS/CMOS basic cell structure which can be used as BiCMOS or CMOS gates, which go to the wiring channels, was developed. The area efficiency of the developed basic cell is 16% better than that of the conventional basic cell, as got from design automation experience, etc. The wiring method of the power supply reinforcement lines of the third metal layer in a large chip was examined from the viewpoint of the number of useful basic cells. As a result, by locating the reinforcement lines at every basic cell, the number of useful basic cells is about 14% more than that of another method in which the reinforcement lines are located at certain intervals of basic cells. Propagation delay time of the 2-input NAND is 190 ps at fan out 10 load. Under a light load, a pure CMOS NAND is faster, achieving a 140 ps gate delay at fan out 2 load. This gate array family can be applied to high speed processors.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_11_3749/_p

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@ARTICLE{e74-c_11_3749,
author={Yoji NISHIO, Noriaki OKA, Shigeru TAKAHASHI, Manabu SHIBATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family},
year={1991},
volume={E74-C},
number={11},
pages={3749-3756},
abstract={A mixed BiCMOS/CMOS channelless gate array family with 3-metal-layer wiring using a 5 V version, 0.5 µm BiCMOS technology is discussed. The speed and power performance of CMOS gates are superior to those of BiCMOS gates for light load capacitance. The power-delay product of CMOS gates at light load is 50% less than that of BiCMOS gates. Therefore, by using CMOS and BiCMOS gates selectively according to the weight of the capacitance load, the performance of the BiCMOS gate array is enhanced. Then, a new mixed BiCMOS/CMOS basic cell structure which can be used as BiCMOS or CMOS gates, which go to the wiring channels, was developed. The area efficiency of the developed basic cell is 16% better than that of the conventional basic cell, as got from design automation experience, etc. The wiring method of the power supply reinforcement lines of the third metal layer in a large chip was examined from the viewpoint of the number of useful basic cells. As a result, by locating the reinforcement lines at every basic cell, the number of useful basic cells is about 14% more than that of another method in which the reinforcement lines are located at certain intervals of basic cells. Propagation delay time of the 2-input NAND is 190 ps at fan out 10 load. Under a light load, a pure CMOS NAND is faster, achieving a 140 ps gate delay at fan out 2 load. This gate array family can be applied to high speed processors.},
keywords={},
doi={},
ISSN={},
month={November},}

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TY - JOUR
TI - A Master Chip Design of 0.5 µm Mixed BiCMOS/CMOS Channelless Gate Array Family
T2 - IEICE TRANSACTIONS on Electronics
SP - 3749
EP - 3756
AU - Yoji NISHIO
AU - Noriaki OKA
AU - Shigeru TAKAHASHI
AU - Manabu SHIBATA
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1991
AB - A mixed BiCMOS/CMOS channelless gate array family with 3-metal-layer wiring using a 5 V version, 0.5 µm BiCMOS technology is discussed. The speed and power performance of CMOS gates are superior to those of BiCMOS gates for light load capacitance. The power-delay product of CMOS gates at light load is 50% less than that of BiCMOS gates. Therefore, by using CMOS and BiCMOS gates selectively according to the weight of the capacitance load, the performance of the BiCMOS gate array is enhanced. Then, a new mixed BiCMOS/CMOS basic cell structure which can be used as BiCMOS or CMOS gates, which go to the wiring channels, was developed. The area efficiency of the developed basic cell is 16% better than that of the conventional basic cell, as got from design automation experience, etc. The wiring method of the power supply reinforcement lines of the third metal layer in a large chip was examined from the viewpoint of the number of useful basic cells. As a result, by locating the reinforcement lines at every basic cell, the number of useful basic cells is about 14% more than that of another method in which the reinforcement lines are located at certain intervals of basic cells. Propagation delay time of the 2-input NAND is 190 ps at fan out 10 load. Under a light load, a pure CMOS NAND is faster, achieving a 140 ps gate delay at fan out 2 load. This gate array family can be applied to high speed processors.
ER -