This paper proposes the design of a matrix multiply-addition VLSI processor (MMP) for minimum-delaytime inverse dynamics computation based on linear array architecture. The MMP mainly consists of four multiply-adders, thus performing 4
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Somchai KITTICHAIKOONKIT, Michitaka KAMEYAMA, Tatsuo HIGUCHI, "Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation" in IEICE TRANSACTIONS on Electronics,
vol. E74-C, no. 11, pp. 3819-3828, November 1991, doi: .
Abstract: This paper proposes the design of a matrix multiply-addition VLSI processor (MMP) for minimum-delaytime inverse dynamics computation based on linear array architecture. The MMP mainly consists of four multiply-adders, thus performing 4
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e74-c_11_3819/_p
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@ARTICLE{e74-c_11_3819,
author={Somchai KITTICHAIKOONKIT, Michitaka KAMEYAMA, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation},
year={1991},
volume={E74-C},
number={11},
pages={3819-3828},
abstract={This paper proposes the design of a matrix multiply-addition VLSI processor (MMP) for minimum-delaytime inverse dynamics computation based on linear array architecture. The MMP mainly consists of four multiply-adders, thus performing 4
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - Design of a Matrix Multiply-Addition VLSI Processor for Robot Inverse Dynamics Computation
T2 - IEICE TRANSACTIONS on Electronics
SP - 3819
EP - 3828
AU - Somchai KITTICHAIKOONKIT
AU - Michitaka KAMEYAMA
AU - Tatsuo HIGUCHI
PY - 1991
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E74-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1991
AB - This paper proposes the design of a matrix multiply-addition VLSI processor (MMP) for minimum-delaytime inverse dynamics computation based on linear array architecture. The MMP mainly consists of four multiply-adders, thus performing 4
ER -