IEICE TRANSACTIONS on Electronics
A Line-Mode Test with Data Register for ULSI Memory Architecture
Summary :
We propose an advanced hyper parallel testing method which improves the line-mode test method by adding data inversion registers which we call the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive and practical test patterns under the hyper parallel condition. The testing time for fixed data patterns are reduced by 1/1900 (all-0/1, checker board, and etc.). Moreover, the ALT can be applicable to the continuous patterns (march, walking, and etc.). The ALT improved from the line-mode test with registers and comparators (LTR) is able to applicable to the most test patterns and to reduce the testing time remarkably, and is suitable for the ULSI memories.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E76-C No.11 pp.1595-1603
- Publication Date
- 1993/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on LSI Memories)
- Category
- DRAM
Authors
Keyword
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Tsukasa OOISHI, Masaki TSUKUDE, Kazutani ARIMOTO, Yoshio MATSUDA, Kazuyasu FUJISHIMA, "A Line-Mode Test with Data Register for ULSI Memory Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 11, pp. 1595-1603, November 1993, doi: .
Abstract: We propose an advanced hyper parallel testing method which improves the line-mode test method by adding data inversion registers which we call the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive and practical test patterns under the hyper parallel condition. The testing time for fixed data patterns are reduced by 1/1900 (all-0/1, checker board, and etc.). Moreover, the ALT can be applicable to the continuous patterns (march, walking, and etc.). The ALT improved from the line-mode test with registers and comparators (LTR) is able to applicable to the most test patterns and to reduce the testing time remarkably, and is suitable for the ULSI memories.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_11_1595/_p
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@ARTICLE{e76-c_11_1595,
author={Tsukasa OOISHI, Masaki TSUKUDE, Kazutani ARIMOTO, Yoshio MATSUDA, Kazuyasu FUJISHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Line-Mode Test with Data Register for ULSI Memory Architecture},
year={1993},
volume={E76-C},
number={11},
pages={1595-1603},
abstract={We propose an advanced hyper parallel testing method which improves the line-mode test method by adding data inversion registers which we call the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive and practical test patterns under the hyper parallel condition. The testing time for fixed data patterns are reduced by 1/1900 (all-0/1, checker board, and etc.). Moreover, the ALT can be applicable to the continuous patterns (march, walking, and etc.). The ALT improved from the line-mode test with registers and comparators (LTR) is able to applicable to the most test patterns and to reduce the testing time remarkably, and is suitable for the ULSI memories.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Line-Mode Test with Data Register for ULSI Memory Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1595
EP - 1603
AU - Tsukasa OOISHI
AU - Masaki TSUKUDE
AU - Kazutani ARIMOTO
AU - Yoshio MATSUDA
AU - Kazuyasu FUJISHIMA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1993
AB - We propose an advanced hyper parallel testing method which improves the line-mode test method by adding data inversion registers which we call the Advanced Line-mode Test (ALT). This testing method has the same testing capability as the conventional bit-by-bit and multi-bit test method (MBT), because it enables the application of a high sensitive and practical test patterns under the hyper parallel condition. The testing time for fixed data patterns are reduced by 1/1900 (all-0/1, checker board, and etc.). Moreover, the ALT can be applicable to the continuous patterns (march, walking, and etc.). The ALT improved from the line-mode test with registers and comparators (LTR) is able to applicable to the most test patterns and to reduce the testing time remarkably, and is suitable for the ULSI memories.
ER -
English
