Proposed Optoelectronic Cascadable Multiplier on GaAs LSI

Kazutoshi NAKAJIMA; Yoshihiko MIZUSHIMA

Proposed Optoelectronic Cascadable Multiplier on GaAs LSI

Kazutoshi NAKAJIMA, Yoshihiko MIZUSHIMA

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An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.1 pp.118-123

Publication Date: 1993/01/25

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Type of Manuscript: Special Section PAPER (Special Issue on Opto-Electronics and LSI)

Category: Integration of Opto-Electronics and LSI Technologies

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Kazutoshi NAKAJIMA, Yoshihiko MIZUSHIMA, "Proposed Optoelectronic Cascadable Multiplier on GaAs LSI" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 1, pp. 118-123, January 1993, doi: .
Abstract: An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_1_118/_p

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@ARTICLE{e76-c_1_118,
author={Kazutoshi NAKAJIMA, Yoshihiko MIZUSHIMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Proposed Optoelectronic Cascadable Multiplier on GaAs LSI},
year={1993},
volume={E76-C},
number={1},
pages={118-123},
abstract={An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.},
keywords={},
doi={},
ISSN={},
month={January},}

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TY - JOUR
TI - Proposed Optoelectronic Cascadable Multiplier on GaAs LSI
T2 - IEICE TRANSACTIONS on Electronics
SP - 118
EP - 123
AU - Kazutoshi NAKAJIMA
AU - Yoshihiko MIZUSHIMA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1993
AB - An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.
ER -