We propose a burst optical packet generator based on a novel photonic parallel-to-serial conversion scheme, and demonstrate 40-Gbit/s 16-bit optical packet generation from 16-ch parallel low-voltage TTL data streams. It consists of electrical 4:1 parallel-to-serial converters that employ InP metal-semiconductor-metal photodetectors, and an optical time-domain multiplexer with electroabsorption modulators. The proposed optical packet generator is suitable for burst optical packet generation and overcomes the electronic bandwidth limitation, which is prerequisite for achieving high-speed photonic packet switched networks. In addition, it can be driven by simple low-cost low-power CMOS logic circuits, and is compact and extensible in terms of the number of input channels due to the effective combination of electrical and optical multiplexing.

One-dimentional equivalent circuit model of a heterostructure InAlAs/InGaAs/InP metal-semiconductor-metal photodetector is discussed. In this photodetector, InGaAs is used as an optical absorption layer and the InAlAs is used for Schottky barrier enhanement. The measured S11 parameter deviates from equi-resistance lines on the Smith chart, indicating the equivalent circuit is different from the conventional equivalent circuit using a series resistance, a depletion region capacitance and a depletion region resistance. The difference is due to band discontinuity at the heterojunctions, and we propose a equivalent circuit taking account of the band discontinuity. The band discontinuity is expressed by parallel combination of a resistance and a capacitance. The measured S11 parameter can be fitted well with the calculated S11 parameter from the proposed equivalent circuit, and we can successfully extract the device parameters from the fitted curve.

An integrated optoelectronic multiplier based on GaAs optoelectronic device technology, is proposed. The key element is an optoelectronic half-adder logic gate, which is composed of only two GaAs metal-semiconductor-metal photodetectors (MSM-PD's). It operates with a single clock delay, less than 100 ps. An optoelectronic full-adder and a multiplier are also composed of half-adders and surface-emitting laser-diodes (SEL's). Cascadable gates with optical interconnections are integrated. Utilizing improved device fabrication technology, an optoelectronic high-speed multiplier with a minimum number of gates will be realized in LSI.