This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 32
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Shoji KAWAHITO, Yasuhiro MITSUI, Tetsuro NAKAMURA, "VLSI-Oriented Multiple-Valued Current-Mode Arithmetic Circuits Using Redundant Number Representations" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 3, pp. 446-454, March 1993, doi: .
Abstract: This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 32
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_3_446/_p
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@ARTICLE{e76-c_3_446,
author={Shoji KAWAHITO, Yasuhiro MITSUI, Tetsuro NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={VLSI-Oriented Multiple-Valued Current-Mode Arithmetic Circuits Using Redundant Number Representations},
year={1993},
volume={E76-C},
number={3},
pages={446-454},
abstract={This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 32
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - VLSI-Oriented Multiple-Valued Current-Mode Arithmetic Circuits Using Redundant Number Representations
T2 - IEICE TRANSACTIONS on Electronics
SP - 446
EP - 454
AU - Shoji KAWAHITO
AU - Yasuhiro MITSUI
AU - Tetsuro NAKAMURA
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 1993
AB - This paper presents a VLSI-oriented arithmetic design method using a radix-2 redundant number representation with digit set {0, 1, 2} and multiple-valued current-mode (MVCM) circuit technology. We propose a carry-propagation-free (CPF) parallel addition method with redundant digit set {0, 1, 2} which is suitable for the design with MVCM circuits. Several types of CPF parallel adders are compared and the proposed CPF parallel adder with MVCM circuits offers the best total performance with respect to speed, complexity, and power dissipation. The designed basic arithmetic circuits has sufficient noise immunity to the supply voltage fluctuation which is important for stable operations of the VLSI circuits. The CPF parallel adder is effectively used as the reduction scheme of partial products in a high-speed compact multiplier. For example, the designed 32
ER -