High-Speed Circuit Techniques for 1 to 5 V Operating Memories

Tomoaki YABE

Summary :

This paper describes high speed circuit techniques for 1 to 5 V operating memories, with special emphasis on SRAM. For achieving large supply voltage margin and high speed compatibly, two novel circuit schemes are proposed; one is Switched Delay Line Pulse Generator (SDLPG), which is a new Address Transition Detect (ATD) pulse generating scheme and the other is Resistor Inserted Current mirror Sense Amplifier (RICSA). In this scheme, critical path of ATD pulse is switched between CR delay line and CMOS gate delay line depending on supply voltage. As a result, ATD pulse width can be tuned to be dominated by CR delay line propagated pulse at high V_cc region and by CMOS gate chain propagated one at low V_cc region. In SDLPG V_cc dependence of ATD pulse width can be adjusted to minimum value for stable operation at both low and high end of target operating voltage region, which leads to high-speed memory operation without excess ATD pulse width. RICSA is a simple circuit scheme modifying current mirror sense amplifier with current limitting resistor inserted between the common source node of two driver NMOSFETs and the drain node of the switch NMOSFET. This technique inproves poor sensitivity of conventional current mirror sense amplifier when common mode input voltage near V_cc is applied, which offers a suitable sense amplifier for 15 V operating SRAM. By applying these techniques and 1 V operating cell techniques, SRAM with high-speed operation in 1 to 5 V range is realized. They are also applicable for other low-voltage memories such as DRAM and EPROM.

• Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.5 pp.708-713
• Publication Date: 1993/05/25
• Type of Manuscript: Special Section PAPER (Special Section on Low-Power and Low-Voltage Integrated Circuits)

Authors

Tomoaki YABE

Keyword

CMOS memory,  SRAM ATD sense-amplifier