In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.

New concept of CMOS nonvolatile memory is presented with demonstration of cell implementations. The memory cell, which is a comparator basically, makes use of comparator offset for storage quantity and the FN stress phenomena for cell programming. We also propose the stress-packet operation which is the relevant programming method to finely control the offset of the memory cell. The memory cell is multiple-time programmable while it is implemented in a standard CMOS process. We fabricated the memory cell arrays of the latch comparator and demonstrated that it is rewritten several times. We also investigated the reliability of cell data retention by monitoring programmed offsets for several months.

This paper describes high speed circuit techniques for 1 to 5 V operating memories, with special emphasis on SRAM. For achieving large supply voltage margin and high speed compatibly, two novel circuit schemes are proposed; one is Switched Delay Line Pulse Generator (SDLPG), which is a new Address Transition Detect (ATD) pulse generating scheme and the other is Resistor Inserted Current mirror Sense Amplifier (RICSA). In this scheme, critical path of ATD pulse is switched between CR delay line and CMOS gate delay line depending on supply voltage. As a result, ATD pulse width can be tuned to be dominated by CR delay line propagated pulse at high Vcc region and by CMOS gate chain propagated one at low Vcc region. In SDLPG Vcc dependence of ATD pulse width can be adjusted to minimum value for stable operation at both low and high end of target operating voltage region, which leads to high-speed memory operation without excess ATD pulse width. RICSA is a simple circuit scheme modifying current mirror sense amplifier with current limitting resistor inserted between the common source node of two driver NMOSFETs and the drain node of the switch NMOSFET. This technique inproves poor sensitivity of conventional current mirror sense amplifier when common mode input voltage near Vcc is applied, which offers a suitable sense amplifier for 15 V operating SRAM. By applying these techniques and 1 V operating cell techniques, SRAM with high-speed operation in 1 to 5 V range is realized. They are also applicable for other low-voltage memories such as DRAM and EPROM.