IEICE TRANSACTIONS on Electronics
Simulation-Based Understanding of “Charge-Sharing Phenomenon” Induced by Heavy-Ion Incident on a 65nm Bulk CMOS Memory Circuit
Summary :
In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E105-C No.1 pp.47-50
- Publication Date
- 2022/01/01
- Publicized
- 2021/08/05
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.2021ECS6008
- Type of Manuscript
- BRIEF PAPER
- Category
- Electronic Circuits
Authors
Akifumi MARU
JAXA,Tokyo Institute of Technology
Akifumi MATSUDA
Tokyo Institute of Technology
Satoshi KUBOYAMA
JAXA
Mamoru YOSHIMOTO
Tokyo Institute of Technology
Keyword
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Akifumi MARU, Akifumi MATSUDA, Satoshi KUBOYAMA, Mamoru YOSHIMOTO, "Simulation-Based Understanding of “Charge-Sharing Phenomenon” Induced by Heavy-Ion Incident on a 65nm Bulk CMOS Memory Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E105-C, no. 1, pp. 47-50, January 2022, doi: 10.1587/transele.2021ECS6008.
Abstract: In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2021ECS6008/_p
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@ARTICLE{e105-c_1_47,
author={Akifumi MARU, Akifumi MATSUDA, Satoshi KUBOYAMA, Mamoru YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Simulation-Based Understanding of “Charge-Sharing Phenomenon” Induced by Heavy-Ion Incident on a 65nm Bulk CMOS Memory Circuit},
year={2022},
volume={E105-C},
number={1},
pages={47-50},
abstract={In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.},
keywords={},
doi={10.1587/transele.2021ECS6008},
ISSN={1745-1353},
month={January},}
Copy
TY - JOUR
TI - Simulation-Based Understanding of “Charge-Sharing Phenomenon” Induced by Heavy-Ion Incident on a 65nm Bulk CMOS Memory Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 47
EP - 50
AU - Akifumi MARU
AU - Akifumi MATSUDA
AU - Satoshi KUBOYAMA
AU - Mamoru YOSHIMOTO
PY - 2022
DO - 10.1587/transele.2021ECS6008
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E105-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2022
AB - In order to expect the single event occurrence on highly integrated CMOS memory circuit, quantitative evaluation of charge sharing between memory cells is needed. In this study, charge sharing area induced by heavy ion incident is quantitatively calculated by using device-simulation-based method. The validity of this method is experimentally confirmed using the charged heavy ion accelerator.
ER -
English
