Design Techniques for High-Throughput BiCMOS Self-Timed SRAM's

Koichi YOKOMIZO; Kuniyoshi NAITO

Design Techniques for High-Throughput BiCMOS Self-Timed SRAM's

Koichi YOKOMIZO, Kuniyoshi NAITO

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This paper describes design techniques for a high-throughput BiCMOS self-timed SRAM. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192 9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-µm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency.

Publication: IEICE TRANSACTIONS on Electronics Vol.E76-C No.5 pp.824-829

Publication Date: 1993/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1992 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.28, No.4 April 1993))

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Koichi YOKOMIZO
Kuniyoshi NAITO

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Koichi YOKOMIZO, Kuniyoshi NAITO, "Design Techniques for High-Throughput BiCMOS Self-Timed SRAM's" in IEICE TRANSACTIONS on Electronics, vol. E76-C, no. 5, pp. 824-829, May 1993, doi: .
Abstract: This paper describes design techniques for a high-throughput BiCMOS self-timed SRAM. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192 9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-µm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_5_824/_p

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@ARTICLE{e76-c_5_824,
author={Koichi YOKOMIZO, Kuniyoshi NAITO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design Techniques for High-Throughput BiCMOS Self-Timed SRAM's},
year={1993},
volume={E76-C},
number={5},
pages={824-829},
abstract={This paper describes design techniques for a high-throughput BiCMOS self-timed SRAM. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192 9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-µm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - Design Techniques for High-Throughput BiCMOS Self-Timed SRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 824
EP - 829
AU - Koichi YOKOMIZO
AU - Kuniyoshi NAITO
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1993
AB - This paper describes design techniques for a high-throughput BiCMOS self-timed SRAM. A new BiCMOS read circuit using a pipelined read architecture and a BiCMOS complementary clocked driver (BCCD) are proposed to reduce the operating cycle time. A 8192 9-b dual-port self-timed SRAM designed using the proposed techniques achieved a clock cycle time of 3.0 ns, that is, a 333-MHz operating frequency, by SPICE simulation on model parameters for 0.8-µm BiCMOS technology. A high-speed built-in self-test (BIST) circuit was studied and designed for the 3.0-ns cycle SRAM. It is confirmed that the BIST circuit allows the 3.0-ns cycle SRAM to test at its maximum operating frequency.
ER -