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Osamu MATSUDA, Shin-ichiro HAYANO, Takao TAKEUCHI, Hideki KITAHATA, Hisashi TAKEMURA, Tsutomu TASHIRO, "A Si Bipolar 1.4-GHz Time Space Switch LSI for B-ISDN" in IEICE TRANSACTIONS on Electronics,
vol. E76-C, no. 5, pp. 858-862, May 1993, doi: .
Abstract: A 155-Mb/s 3232 Si bipolar switch LSI is designed and implemented for a wide application in the broad-band ISDN. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies are newly developed for the LSI, namely, 1) active pull-down circuit with an embedded bias circuit in each gate, and 2) modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area are reduced to 60% and 70%, respectively, of what is expected when conventional ECL technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e76-c_5_858/_p
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@ARTICLE{e76-c_5_858,
author={Osamu MATSUDA, Shin-ichiro HAYANO, Takao TAKEUCHI, Hideki KITAHATA, Hisashi TAKEMURA, Tsutomu TASHIRO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Si Bipolar 1.4-GHz Time Space Switch LSI for B-ISDN},
year={1993},
volume={E76-C},
number={5},
pages={858-862},
abstract={A 155-Mb/s 3232 Si bipolar switch LSI is designed and implemented for a wide application in the broad-band ISDN. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies are newly developed for the LSI, namely, 1) active pull-down circuit with an embedded bias circuit in each gate, and 2) modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area are reduced to 60% and 70%, respectively, of what is expected when conventional ECL technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - A Si Bipolar 1.4-GHz Time Space Switch LSI for B-ISDN
T2 - IEICE TRANSACTIONS on Electronics
SP - 858
EP - 862
AU - Osamu MATSUDA
AU - Shin-ichiro HAYANO
AU - Takao TAKEUCHI
AU - Hideki KITAHATA
AU - Hisashi TAKEMURA
AU - Tsutomu TASHIRO
PY - 1993
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E76-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1993
AB - A 155-Mb/s 3232 Si bipolar switch LSI is designed and implemented for a wide application in the broad-band ISDN. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies are newly developed for the LSI, namely, 1) active pull-down circuit with an embedded bias circuit in each gate, and 2) modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area are reduced to 60% and 70%, respectively, of what is expected when conventional ECL technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system.
ER -
English
