A Fuzzy Logic Inference Processor

John W. FATTARUSO; Shivaling S. MAHANT-SHETTI; J. Brock BARTON

A Fuzzy Logic Inference Processor

John W. FATTARUSO, Shivaling S. MAHANT-SHETTI, J. Brock BARTON

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A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 µm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 µs.

Publication: IEICE TRANSACTIONS on Electronics Vol.E77-C No.5 pp.727-732

Publication Date: 1994/05/25

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Type of Manuscript: Special Section PAPER (Special Section on the 1993 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.29, No.4 April 1994))

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John W. FATTARUSO
Shivaling S. MAHANT-SHETTI
J. Brock BARTON

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John W. FATTARUSO, Shivaling S. MAHANT-SHETTI, J. Brock BARTON, "A Fuzzy Logic Inference Processor" in IEICE TRANSACTIONS on Electronics, vol. E77-C, no. 5, pp. 727-732, May 1994, doi: .
Abstract: A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 µm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 µs.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e77-c_5_727/_p

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@ARTICLE{e77-c_5_727,
author={John W. FATTARUSO, Shivaling S. MAHANT-SHETTI, J. Brock BARTON, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Fuzzy Logic Inference Processor},
year={1994},
volume={E77-C},
number={5},
pages={727-732},
abstract={A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 µm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 µs.},
keywords={},
doi={},
ISSN={},
month={May},}

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TY - JOUR
TI - A Fuzzy Logic Inference Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 727
EP - 732
AU - John W. FATTARUSO
AU - Shivaling S. MAHANT-SHETTI
AU - J. Brock BARTON
PY - 1994
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E77-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 1994
AB - A mixed analog-digital fuzzy logic inference engine chip fabricated in an 0.8 µm CMOS process is described. Interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules, including a center-of-mass defuzzification, may be computed in 2 µs.
ER -