IEICE TRANSACTIONS on Electronics
An ATM Chip Set for High Performance Computer Interfaces, Affording over 100 Mbps Sustained Throughput
Summary :
The transmission and processing of multimedia information requires a high-speed communications network infrastructure. This is especially true for the networks between the user's computer and the information highway. An Ethernet LAN is widely used for these networks, but it has limited throughput. Asynchronous Transfer Mode (ATM) LAN technology is a promising approach to overcome this limitation. We have developed a chip set which can be used to connect personal computers (PCs) and workstations (WSs) to a 156-Mbps ATM LAN. The advanced architecture, optimized performance and efficient buffer management enables a sustained more than 100 Mbps transfer speed to be obtained. The chip set is implemented in a 0.8 µm triple metal-layer CMOS process to integrate total 460 K transistors and consumes total 4 W at 5 V.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E78-C No.12 pp.1738-1745
- Publication Date
- 1995/12/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-power Analog, Digital LSIs and ASICs for Multimedia)
- Category
Authors
Yasuharu TOMIMITSU
Satoru KAWANAGO
Hirotaka YAMANE
Hideki KOBUNAYA
Shoji OHGANE
Nobuyuki MIZUKOSHI
Hiroshi SUZUKI
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Yasuharu TOMIMITSU, Satoru KAWANAGO, Hirotaka YAMANE, Hideki KOBUNAYA, Shoji OHGANE, Nobuyuki MIZUKOSHI, Hiroshi SUZUKI, "An ATM Chip Set for High Performance Computer Interfaces, Affording over 100 Mbps Sustained Throughput" in IEICE TRANSACTIONS on Electronics,
vol. E78-C, no. 12, pp. 1738-1745, December 1995, doi: .
Abstract: The transmission and processing of multimedia information requires a high-speed communications network infrastructure. This is especially true for the networks between the user's computer and the information highway. An Ethernet LAN is widely used for these networks, but it has limited throughput. Asynchronous Transfer Mode (ATM) LAN technology is a promising approach to overcome this limitation. We have developed a chip set which can be used to connect personal computers (PCs) and workstations (WSs) to a 156-Mbps ATM LAN. The advanced architecture, optimized performance and efficient buffer management enables a sustained more than 100 Mbps transfer speed to be obtained. The chip set is implemented in a 0.8 µm triple metal-layer CMOS process to integrate total 460 K transistors and consumes total 4 W at 5 V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_12_1738/_p
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@ARTICLE{e78-c_12_1738,
author={Yasuharu TOMIMITSU, Satoru KAWANAGO, Hirotaka YAMANE, Hideki KOBUNAYA, Shoji OHGANE, Nobuyuki MIZUKOSHI, Hiroshi SUZUKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={An ATM Chip Set for High Performance Computer Interfaces, Affording over 100 Mbps Sustained Throughput},
year={1995},
volume={E78-C},
number={12},
pages={1738-1745},
abstract={The transmission and processing of multimedia information requires a high-speed communications network infrastructure. This is especially true for the networks between the user's computer and the information highway. An Ethernet LAN is widely used for these networks, but it has limited throughput. Asynchronous Transfer Mode (ATM) LAN technology is a promising approach to overcome this limitation. We have developed a chip set which can be used to connect personal computers (PCs) and workstations (WSs) to a 156-Mbps ATM LAN. The advanced architecture, optimized performance and efficient buffer management enables a sustained more than 100 Mbps transfer speed to be obtained. The chip set is implemented in a 0.8 µm triple metal-layer CMOS process to integrate total 460 K transistors and consumes total 4 W at 5 V.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - An ATM Chip Set for High Performance Computer Interfaces, Affording over 100 Mbps Sustained Throughput
T2 - IEICE TRANSACTIONS on Electronics
SP - 1738
EP - 1745
AU - Yasuharu TOMIMITSU
AU - Satoru KAWANAGO
AU - Hirotaka YAMANE
AU - Hideki KOBUNAYA
AU - Shoji OHGANE
AU - Nobuyuki MIZUKOSHI
AU - Hiroshi SUZUKI
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1995
AB - The transmission and processing of multimedia information requires a high-speed communications network infrastructure. This is especially true for the networks between the user's computer and the information highway. An Ethernet LAN is widely used for these networks, but it has limited throughput. Asynchronous Transfer Mode (ATM) LAN technology is a promising approach to overcome this limitation. We have developed a chip set which can be used to connect personal computers (PCs) and workstations (WSs) to a 156-Mbps ATM LAN. The advanced architecture, optimized performance and efficient buffer management enables a sustained more than 100 Mbps transfer speed to be obtained. The chip set is implemented in a 0.8 µm triple metal-layer CMOS process to integrate total 460 K transistors and consumes total 4 W at 5 V.
ER -
English
