A Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays

Robert J. LANDERS; Shivaling S. MAHANT-SHETTI; Carl LEMONDS

A Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays

Robert J. LANDERS, Shivaling S. MAHANT-SHETTI, Carl LEMONDS

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This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 16-b multiplier operating at 50 MHz in 314 500 µm² in 0.6 µm technology.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.640-644

Publication Date: 1995/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))

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Robert J. LANDERS
Shivaling S. MAHANT-SHETTI
Carl LEMONDS

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Robert J. LANDERS, Shivaling S. MAHANT-SHETTI, Carl LEMONDS, "A Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 6, pp. 640-644, June 1995, doi: .
Abstract: This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 16-b multiplier operating at 50 MHz in 314 500 µm² in 0.6 µm technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_6_640/_p

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@ARTICLE{e78-c_6_640,
author={Robert J. LANDERS, Shivaling S. MAHANT-SHETTI, Carl LEMONDS, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays},
year={1995},
volume={E78-C},
number={6},
pages={640-644},
abstract={This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 16-b multiplier operating at 50 MHz in 314 500 µm² in 0.6 µm technology.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A Multiplexer-Based Architecture for High-Density, Low-Power Gate Arrays
T2 - IEICE TRANSACTIONS on Electronics
SP - 640
EP - 644
AU - Robert J. LANDERS
AU - Shivaling S. MAHANT-SHETTI
AU - Carl LEMONDS
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - This paper presents a novel architecture that provides higher density and lower power dissipation than conventional basecells. The layout of transistors in this small basecell allows the efficient construction of multiplexers with minimal use of programmable layers. The multiplexer can be used to create any 2 input and some 3 input functions in one basecell. Internal fanout, rather than typical output load, defines the size of driver and multiplexer transistors, which can be independently tailored for the desired speed/area/power target. This basecell, which is well suited for implementing datapath elements, has been used to create a 16 16-b multiplier operating at 50 MHz in 314 500 µm² in 0.6 µm technology.
ER -