A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging

Feng CHEN; Bosco H. LEUNG

A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging

Feng CHEN, Bosco H. LEUNG

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A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 µm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 KHz baseband. No tone is observed in the baseband as the amplitude of a 10 KHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply.

Publication: IEICE TRANSACTIONS on Electronics Vol.E78-C No.6 pp.701-708

Publication Date: 1995/06/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1994 VLSI Circuits Symposium (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol. 30, No. 4 April 1995))

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Feng CHEN
Bosco H. LEUNG

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Feng CHEN, Bosco H. LEUNG, "A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging" in IEICE TRANSACTIONS on Electronics, vol. E78-C, no. 6, pp. 701-708, June 1995, doi: .
Abstract: A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 µm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 KHz baseband. No tone is observed in the baseband as the amplitude of a 10 KHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e78-c_6_701/_p

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@ARTICLE{e78-c_6_701,
author={Feng CHEN, Bosco H. LEUNG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging},
year={1995},
volume={E78-C},
number={6},
pages={701-708},
abstract={A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 µm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 KHz baseband. No tone is observed in the baseband as the amplitude of a 10 KHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - A High Resolution Multibit Sigma-Delta Modulator with Individual Level Averaging
T2 - IEICE TRANSACTIONS on Electronics
SP - 701
EP - 708
AU - Feng CHEN
AU - Bosco H. LEUNG
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E78-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1995
AB - A second-order sigma-delta modulator with a 3-b internal quantizer employing the individual level averaging technique has been designed and implemented in a 1.2 µm CMOS technology. Testing results show no observable harmonic distortion components above the noise floor. Peak S/(N+D) ratio of 91 dB and dynamic range of 96 dB have been achieved at a clock rate of 2.56 MHz for a 20 KHz baseband. No tone is observed in the baseband as the amplitude of a 10 KHz input sine wave is reduced from -0.5 dB to -107 dB below the voltage reference. The active area of the prototype chip is 3.1 mm² and it dissipates 67.5 mW of power from a 5 V supply.
ER -