Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells

Toru IWATA; Hiroyuki YAMAUCHI

Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells

Toru IWATA, Hiroyuki YAMAUCHI

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To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.12 pp.1707-1712

Publication Date: 1996/12/25

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Type of Manuscript: Special Section PAPER (Special Issue on Low-Power LSI Technologies)

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Toru IWATA, Hiroyuki YAMAUCHI, "Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 12, pp. 1707-1712, December 1996, doi: .
Abstract: To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_12_1707/_p

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@ARTICLE{e79-c_12_1707,
author={Toru IWATA, Hiroyuki YAMAUCHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells},
year={1996},
volume={E79-C},
number={12},
pages={1707-1712},
abstract={To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - Plate Bumping Leakage Current Measurement Method and Its Application to Data Retention Characteristic Analysis for RJB DRAM Cells
T2 - IEICE TRANSACTIONS on Electronics
SP - 1707
EP - 1712
AU - Toru IWATA
AU - Hiroyuki YAMAUCHI
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 1996
AB - To evaluate DRAM memory-cell data retention characteristics, measuring the leakage current of the individual memory-cell is important. However, the leakage current of a DRAM memory-cell cannot be measured directly, because its value is on the order of femtoamperes. This paper describes a Plate Bumping (PB) method that can measure the leakage current of a specific memory-cell using the relationship between the shifted value of memory-cell-plate potential and the retention period. By using the PB method, it can be confirmed that the leakage current of the short-retention cell (bad cell) depends on its storage-node potential. With regards to cells with "0" data stored in them ("0" cells), it appears that the relaxed junction biasing (RJB) scheme which can extend refresh interval increases the number of misread "0" cells due to the lowering of the sense amplifier's sensing threshold.
ER -