A Current Direction Sense Technique for Multiport SRAM's

Masanori IZUMIKAWA; Masakazu YAMASHINA

A Current Direction Sense Technique for Multiport SRAM's

Masanori IZUMIKAWA, Masakazu YAMASHINA

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This paper describes two techniques for low-power single-end multiport SRAM's: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal. When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%.

Publication: IEICE TRANSACTIONS on Electronics Vol.E79-C No.7 pp.957-962

Publication Date: 1996/07/25

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Type of Manuscript: Special Section PAPER (Special Issue on the 1995 Symposium on VLSI Circuits (Joint Issue with the IEEE Journal of Solid-State Circuits, Vol.31, No.4 April 1996))

Category: Memory

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Masanori IZUMIKAWA
Masakazu YAMASHINA

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Masanori IZUMIKAWA, Masakazu YAMASHINA, "A Current Direction Sense Technique for Multiport SRAM's" in IEICE TRANSACTIONS on Electronics, vol. E79-C, no. 7, pp. 957-962, July 1996, doi: .
Abstract: This paper describes two techniques for low-power single-end multiport SRAM's: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal. When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e79-c_7_957/_p

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@ARTICLE{e79-c_7_957,
author={Masanori IZUMIKAWA, Masakazu YAMASHINA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Current Direction Sense Technique for Multiport SRAM's},
year={1996},
volume={E79-C},
number={7},
pages={957-962},
abstract={This paper describes two techniques for low-power single-end multiport SRAM's: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal. When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%.},
keywords={},
doi={},
ISSN={},
month={July},}

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TY - JOUR
TI - A Current Direction Sense Technique for Multiport SRAM's
T2 - IEICE TRANSACTIONS on Electronics
SP - 957
EP - 962
AU - Masanori IZUMIKAWA
AU - Masakazu YAMASHINA
PY - 1996
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E79-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1996
AB - This paper describes two techniques for low-power single-end multiport SRAM's: a current direction sense circuit and a write bit-line swing control circuit. The sense circuit's input node is clamped at an intermediate voltage level, and the circuit transforms current direction into a logic value. It operates four times faster than a CMOS inverter, when driver sizes are equal. When it is applied to a single-end multiport SRAM, access is accelerated 3.2 times faster than that with a CMOS inverter with no increase in power consumption. The write bit-line swing control circuit reduces the bit-line precharge level within the limit of correct operation by using a memory cell replica. The control circuit reduces power consumption for bit-line driving and pseudoread cell current by 40%.
ER -