IEICE TRANSACTIONS on Electronics
A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
Summary :
Three-dimensional (3-D) instrumentation using an image sequence is a promising instrumentation method for intelligent systems in which accurate 3-D information is required. However, real-time instrumentation is difficult since much computation time and a large memory bandwidth are required. In this paper, a 3-D instrumentation VLSI processor with a concurrent memory-access scheme is proposed. To reduce the access time, frequently used data are stored in a cache register array and are concurrently transferred to processing elements using simple interconnections to the 8-nearest neighbor registers. Based on a row and column memory access pattern, we propose a diagonally interleaved frame memory by which pixel values of a row and column are stored across memory modules. Based on the concurrent memory-access scheme, a 40 GOPS vprocessor is designed and the delay time for the instrumentation is estimated to be 42 ms for a 256
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E80-C No.11 pp.1491-1498
- Publication Date
- 1997/11/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Integrated Electronics
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Seunghwan LEE, Masanori HARIYAMA, Michitaka KAMEYAMA, "A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 11, pp. 1491-1498, November 1997, doi: .
Abstract: Three-dimensional (3-D) instrumentation using an image sequence is a promising instrumentation method for intelligent systems in which accurate 3-D information is required. However, real-time instrumentation is difficult since much computation time and a large memory bandwidth are required. In this paper, a 3-D instrumentation VLSI processor with a concurrent memory-access scheme is proposed. To reduce the access time, frequently used data are stored in a cache register array and are concurrently transferred to processing elements using simple interconnections to the 8-nearest neighbor registers. Based on a row and column memory access pattern, we propose a diagonally interleaved frame memory by which pixel values of a row and column are stored across memory modules. Based on the concurrent memory-access scheme, a 40 GOPS vprocessor is designed and the delay time for the instrumentation is estimated to be 42 ms for a 256
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_11_1491/_p
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@ARTICLE{e80-c_11_1491,
author={Seunghwan LEE, Masanori HARIYAMA, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme},
year={1997},
volume={E80-C},
number={11},
pages={1491-1498},
abstract={Three-dimensional (3-D) instrumentation using an image sequence is a promising instrumentation method for intelligent systems in which accurate 3-D information is required. However, real-time instrumentation is difficult since much computation time and a large memory bandwidth are required. In this paper, a 3-D instrumentation VLSI processor with a concurrent memory-access scheme is proposed. To reduce the access time, frequently used data are stored in a cache register array and are concurrently transferred to processing elements using simple interconnections to the 8-nearest neighbor registers. Based on a row and column memory access pattern, we propose a diagonally interleaved frame memory by which pixel values of a row and column are stored across memory modules. Based on the concurrent memory-access scheme, a 40 GOPS vprocessor is designed and the delay time for the instrumentation is estimated to be 42 ms for a 256
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Three-Dimensional Instrumentation VLSI Processor Based on a Concurrent Memory-Access Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 1491
EP - 1498
AU - Seunghwan LEE
AU - Masanori HARIYAMA
AU - Michitaka KAMEYAMA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1997
AB - Three-dimensional (3-D) instrumentation using an image sequence is a promising instrumentation method for intelligent systems in which accurate 3-D information is required. However, real-time instrumentation is difficult since much computation time and a large memory bandwidth are required. In this paper, a 3-D instrumentation VLSI processor with a concurrent memory-access scheme is proposed. To reduce the access time, frequently used data are stored in a cache register array and are concurrently transferred to processing elements using simple interconnections to the 8-nearest neighbor registers. Based on a row and column memory access pattern, we propose a diagonally interleaved frame memory by which pixel values of a row and column are stored across memory modules. Based on the concurrent memory-access scheme, a 40 GOPS vprocessor is designed and the delay time for the instrumentation is estimated to be 42 ms for a 256
ER -
English
