A low power dual modulus prescaler for frequency synthesizers has been designed in a standard 1.2 µm digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design besides low power consumption: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 200 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. At 195 MHz and 3 V supply, the current consumption of the prescaler is as low as 289 µA, while maximum operating frequencies of 910 MHz at 5 V and 650 MHz at 3 V are achieved.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copy
Francesco PIAZZA, Qiuting HUANG, "A Low Power CMOS Dual Modulus Prescaler for Frequency Synthesizers" in IEICE TRANSACTIONS on Electronics,
vol. E80-C, no. 2, pp. 314-319, February 1997, doi: .
Abstract: A low power dual modulus prescaler for frequency synthesizers has been designed in a standard 1.2 µm digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design besides low power consumption: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 200 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. At 195 MHz and 3 V supply, the current consumption of the prescaler is as low as 289 µA, while maximum operating frequencies of 910 MHz at 5 V and 650 MHz at 3 V are achieved.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e80-c_2_314/_p
Copy
@ARTICLE{e80-c_2_314,
author={Francesco PIAZZA, Qiuting HUANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low Power CMOS Dual Modulus Prescaler for Frequency Synthesizers},
year={1997},
volume={E80-C},
number={2},
pages={314-319},
abstract={A low power dual modulus prescaler for frequency synthesizers has been designed in a standard 1.2 µm digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design besides low power consumption: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 200 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. At 195 MHz and 3 V supply, the current consumption of the prescaler is as low as 289 µA, while maximum operating frequencies of 910 MHz at 5 V and 650 MHz at 3 V are achieved.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A Low Power CMOS Dual Modulus Prescaler for Frequency Synthesizers
T2 - IEICE TRANSACTIONS on Electronics
SP - 314
EP - 319
AU - Francesco PIAZZA
AU - Qiuting HUANG
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E80-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 1997
AB - A low power dual modulus prescaler for frequency synthesizers has been designed in a standard 1.2 µm digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design besides low power consumption: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 200 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. At 195 MHz and 3 V supply, the current consumption of the prescaler is as low as 289 µA, while maximum operating frequencies of 910 MHz at 5 V and 650 MHz at 3 V are achieved.
ER -