Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.

This paper describes a Variable Threshold-voltage CMOS technology (VTCMOS) which controls the threshold voltage (VTH) by means of substrate bias control. Circuit techniques to combine a switch circuit for an active mode and a pump circuit for a standby mode are presented. Design considerations, such as latch-up immunity and upper limit of reverse substrate bias, are discussed. Experimental results obtained from chips fabricated in a 0.3 µm VTCMOS technology are reported. VTH controllability including temperature dependence and influence on short channel effect, power penalty caused by the control circuit, substrate current dependence at low VTH, and substrate noise influence on circuit performance are investigated. A scaling theory is also presented for use in the discussion of future possibilities and problems involved in this technology.

A low power dual modulus prescaler for frequency synthesizers has been designed in a standard 1.2 µm digital CMOS process using enhancement source coupled logic (ESCL). Being a differential low amplitude current mode logic, ESCL has two interesting characteristics for this design besides low power consumption: the low noise performance, that allows this circuit to be on the same chip with sensitive analog circuitry, and the ability to run with a 200 mV sinusoidal signal as generated from an LC oscillator without the need of a clock amplifier. At 195 MHz and 3 V supply, the current consumption of the prescaler is as low as 289 µA, while maximum operating frequencies of 910 MHz at 5 V and 650 MHz at 3 V are achieved.