IEICE TRANSACTIONS on Electronics
Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs
Summary :
In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E81-C No.9 pp.1455-1462
- Publication Date
- 1998/09/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Issue on Novel VLSI Processor Architectures)
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Taku OHSAWA, Koji KAI, Kazuaki MURAKAMI, "Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs" in IEICE TRANSACTIONS on Electronics,
vol. E81-C, no. 9, pp. 1455-1462, September 1998, doi: .
Abstract: In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e81-c_9_1455/_p
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@ARTICLE{e81-c_9_1455,
author={Taku OHSAWA, Koji KAI, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs},
year={1998},
volume={E81-C},
number={9},
pages={1455-1462},
abstract={In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.},
keywords={},
doi={},
ISSN={},
month={September},}
Copy
TY - JOUR
TI - Evaluating DRAM Refresh Architectures for Merged DRAM/Logic LSIs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1455
EP - 1462
AU - Taku OHSAWA
AU - Koji KAI
AU - Kazuaki MURAKAMI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E81-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1998
AB - In merged DRAM/logic LSIs, it is necessary to reduce the number of DRAM refreshes because of higher heat dissipation caused by the logic portion on the same chip. In order to overcome this problem, we propose several DRAM refresh architectures. The basic is to eliminate unnecessary DRAM refreshes. In addition to this, we propose a method for reducing the number of DRAM refreshes by relocating data. In order to evaluate these architectures and method, we have estimated the DRAM refresh count in executing benchmark programs under several models which simulate each combination of them. As a result, in the most effective combination, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most of benchmark programs. In addition to it, we have taken normal DRAM access into account, even then we have obtained more than 50% reduction for several benchmarks.
ER -
English
