IEICE TRANSACTIONS on Electronics
A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
Summary :
We fabricated a 16-kB cache macro using 0.35-µm quadruple-metal CMOS technology. This is a 285-MHz, two-port 16-kB (512
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E83-C No.1 pp.109-114
- Publication Date
- 2000/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Electronic Circuits
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Kenichi OSADA, Hisayuki HIGUCHI, Koichiro ISHIBASHI, Naotaka HASHIMOTO, Kenji SHIOZAWA, "A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 1, pp. 109-114, January 2000, doi: .
Abstract: We fabricated a 16-kB cache macro using 0.35-µm quadruple-metal CMOS technology. This is a 285-MHz, two-port 16-kB (512
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_1_109/_p
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@ARTICLE{e83-c_1_109,
author={Kenichi OSADA, Hisayuki HIGUCHI, Koichiro ISHIBASHI, Naotaka HASHIMOTO, Kenji SHIOZAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs},
year={2000},
volume={E83-C},
number={1},
pages={109-114},
abstract={We fabricated a 16-kB cache macro using 0.35-µm quadruple-metal CMOS technology. This is a 285-MHz, two-port 16-kB (512
keywords={},
doi={},
ISSN={},
month={January},}
Copy
TY - JOUR
TI - A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs
T2 - IEICE TRANSACTIONS on Electronics
SP - 109
EP - 114
AU - Kenichi OSADA
AU - Hisayuki HIGUCHI
AU - Koichiro ISHIBASHI
AU - Naotaka HASHIMOTO
AU - Kenji SHIOZAWA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2000
AB - We fabricated a 16-kB cache macro using 0.35-µm quadruple-metal CMOS technology. This is a 285-MHz, two-port 16-kB (512
ER -
English
