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A 2-ns-Access, 285-MHz, Two-Port Cache Macro Using Double Global Bit-Line Pairs

Kenichi OSADA, Hisayuki HIGUCHI, Koichiro ISHIBASHI, Naotaka HASHIMOTO, Kenji SHIOZAWA

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Summary :

We fabricated a 16-kB cache macro using 0.35-µm quadruple-metal CMOS technology. This is a 285-MHz, two-port 16-kB (512256 b) cache macro that has a 2-ns access time. This high-speed performance is enabled by a hierarchical bit-line architecture that uses double global bit-line pairs (WGBs), and a high-speed timing-insensitive sense amplifier (ISA) that shortens the access time.

Publication
IEICE TRANSACTIONS on Electronics Vol.E83-C No.1 pp.109-114
Publication Date
2000/01/25
Publicized
Online ISSN
DOI
Type of Manuscript
PAPER
Category
Electronic Circuits

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