IEICE TRANSACTIONS on Electronics
An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core
Summary :
This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E84-C No.2 pp.202-211
- Publication Date
- 2001/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Low-Power High-Performance VLSI Processors and Technologies)
- Category
Authors
Hiroshi SEGAWA
Yoshinori MATSUURA
Satoshi KUMAKI
Tetsuya MATSUMURA
Stefan SCOTZNIOVSKY
Shu MURAYAMA
Tetsuro WADA
Ayako HARADA
Eiji OHARA
Ken-ichi ASANO
Toyohiko YOSHIDA
Yasutaka HORIBA
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Hiroshi SEGAWA, Yoshinori MATSUURA, Satoshi KUMAKI, Tetsuya MATSUMURA, Stefan SCOTZNIOVSKY, Shu MURAYAMA, Tetsuro WADA, Ayako HARADA, Eiji OHARA, Ken-ichi ASANO, Toyohiko YOSHIDA, Yasutaka HORIBA, "An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 202-211, February 2001, doi: .
Abstract: This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_202/_p
Copy
@ARTICLE{e84-c_2_202,
author={Hiroshi SEGAWA, Yoshinori MATSUURA, Satoshi KUMAKI, Tetsuya MATSUMURA, Stefan SCOTZNIOVSKY, Shu MURAYAMA, Tetsuro WADA, Ayako HARADA, Eiji OHARA, Ken-ichi ASANO, Toyohiko YOSHIDA, Yasutaka HORIBA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core},
year={2001},
volume={E84-C},
number={2},
pages={202-211},
abstract={This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - An Embedded Software Scheme for a Real-Time Single-Chip MPEG-2 Encoder System with a VLIW Media Processor Core
T2 - IEICE TRANSACTIONS on Electronics
SP - 202
EP - 211
AU - Hiroshi SEGAWA
AU - Yoshinori MATSUURA
AU - Satoshi KUMAKI
AU - Tetsuya MATSUMURA
AU - Stefan SCOTZNIOVSKY
AU - Shu MURAYAMA
AU - Tetsuro WADA
AU - Ayako HARADA
AU - Eiji OHARA
AU - Ken-ichi ASANO
AU - Toyohiko YOSHIDA
AU - Yasutaka HORIBA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - This paper describes an embedded software scheme for a single-chip MPEG-2 encoder that executes concurrent video, audio, and system encoding in real-time. The software features a scalable module structure, which is hierarchically composed and has expandable plug-in modules. For increased applicability, several task-modules are prepared for the respective video, audio, and system processing. In addition, an effective task management scheme that features polling and interrupt-based task switching has been proposed in order to achieve real-time operation. The software having these features and including all task-modules is implemented on a single media-processor D30V on a single chip MPEG-2 video, audio, and system encoder. This encoder realizes real-time MPEG-2 video encoding, Dolby Digital or MPEG-1 audio encoding, and system encoding that generates TS or PS over 50 Mbps for various applications. Assuming a DVD or DTV encoder system, the software is reconstructed with less than 56.6-kbytes of instruction and 145.6 MIPS performance. The single media-processor with 64-kbytes of instruction RAM and 162 MIPS performance, running at a clock rate of 162 MHz, can successfully accomplish a real-time operation with the proposed embedded software.
ER -
English
