A 4-12 GHz 2 W GaAs HFET Amplifier Using Pre-Matching Circuits for Dual Gate-Bias Feed and Tapered Power Splitting/Combining FETs

Hidenori YUKAWA; Masatoshi NII; Yoshihiro TSUKAHARA; Yukio IKEDA; Yasushi ITOH

A 4-12 GHz 2 W GaAs HFET Amplifier Using Pre-Matching Circuits for Dual Gate-Bias Feed and Tapered Power Splitting/Combining FETs

Hidenori YUKAWA, Masatoshi NII, Yoshihiro TSUKAHARA, Yukio IKEDA, Yasushi ITOH

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A 4-12 GHz 2 W GaAs HFET amplifier has been developed. It employs two novel circuit design techniques. One is a pre-matching circuit for dual gate-bias feed. It is comprised of two shunt LCR circuits, which makes dual gate-bias feed possible. The other one is a tapered power splitting/combining FET (tapered PS/PC FET), which makes amplitude and phase imbalance between FET cells small over a wide bandwidth. In this paper, the schematic diagram and impedance characteristic of the pre-matching circuit for dual gate-bias feed are described first, showing the conditions that the impedance of FETs becomes purely resistive. Then the amplitude and phase imbalance between FET cells are compared by electromagnetic simulation for both the conventional and tapered PS/PC FETs, demonstrating that the tapered PS/PC FET has smaller amplitude and phase imbalance. Furthermore, the MSG/MAG are compared by experiment for both FETs, confirming that the tapered PS/PC FET has higher MSG/MAG. Finally, the design, fabrication, and performance of the 4-12 GHz 2 W GaAs HFET amplifier using the pre-matching circuit for dual gate-bias feed and tapered PS/PC FETs are presented to make sure that two novel circuit design techniques introduced in this paper are useful for the design of wideband lossy match power amplifiers.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.12 pp.2029-2035

Publication Date: 2002/12/01

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Type of Manuscript: Special Section PAPER (Special Issue on Low-Distortion,High-Power,High-Efficiency Active Device and Circuit Technology)

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Hidenori YUKAWA, Masatoshi NII, Yoshihiro TSUKAHARA, Yukio IKEDA, Yasushi ITOH, "A 4-12 GHz 2 W GaAs HFET Amplifier Using Pre-Matching Circuits for Dual Gate-Bias Feed and Tapered Power Splitting/Combining FETs" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 12, pp. 2029-2035, December 2002, doi: .
Abstract: A 4-12 GHz 2 W GaAs HFET amplifier has been developed. It employs two novel circuit design techniques. One is a pre-matching circuit for dual gate-bias feed. It is comprised of two shunt LCR circuits, which makes dual gate-bias feed possible. The other one is a tapered power splitting/combining FET (tapered PS/PC FET), which makes amplitude and phase imbalance between FET cells small over a wide bandwidth. In this paper, the schematic diagram and impedance characteristic of the pre-matching circuit for dual gate-bias feed are described first, showing the conditions that the impedance of FETs becomes purely resistive. Then the amplitude and phase imbalance between FET cells are compared by electromagnetic simulation for both the conventional and tapered PS/PC FETs, demonstrating that the tapered PS/PC FET has smaller amplitude and phase imbalance. Furthermore, the MSG/MAG are compared by experiment for both FETs, confirming that the tapered PS/PC FET has higher MSG/MAG. Finally, the design, fabrication, and performance of the 4-12 GHz 2 W GaAs HFET amplifier using the pre-matching circuit for dual gate-bias feed and tapered PS/PC FETs are presented to make sure that two novel circuit design techniques introduced in this paper are useful for the design of wideband lossy match power amplifiers.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_12_2029/_p

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@ARTICLE{e85-c_12_2029,
author={Hidenori YUKAWA, Masatoshi NII, Yoshihiro TSUKAHARA, Yukio IKEDA, Yasushi ITOH, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 4-12 GHz 2 W GaAs HFET Amplifier Using Pre-Matching Circuits for Dual Gate-Bias Feed and Tapered Power Splitting/Combining FETs},
year={2002},
volume={E85-C},
number={12},
pages={2029-2035},
abstract={A 4-12 GHz 2 W GaAs HFET amplifier has been developed. It employs two novel circuit design techniques. One is a pre-matching circuit for dual gate-bias feed. It is comprised of two shunt LCR circuits, which makes dual gate-bias feed possible. The other one is a tapered power splitting/combining FET (tapered PS/PC FET), which makes amplitude and phase imbalance between FET cells small over a wide bandwidth. In this paper, the schematic diagram and impedance characteristic of the pre-matching circuit for dual gate-bias feed are described first, showing the conditions that the impedance of FETs becomes purely resistive. Then the amplitude and phase imbalance between FET cells are compared by electromagnetic simulation for both the conventional and tapered PS/PC FETs, demonstrating that the tapered PS/PC FET has smaller amplitude and phase imbalance. Furthermore, the MSG/MAG are compared by experiment for both FETs, confirming that the tapered PS/PC FET has higher MSG/MAG. Finally, the design, fabrication, and performance of the 4-12 GHz 2 W GaAs HFET amplifier using the pre-matching circuit for dual gate-bias feed and tapered PS/PC FETs are presented to make sure that two novel circuit design techniques introduced in this paper are useful for the design of wideband lossy match power amplifiers.},
keywords={},
doi={},
ISSN={},
month={December},}

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TY - JOUR
TI - A 4-12 GHz 2 W GaAs HFET Amplifier Using Pre-Matching Circuits for Dual Gate-Bias Feed and Tapered Power Splitting/Combining FETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 2029
EP - 2035
AU - Hidenori YUKAWA
AU - Masatoshi NII
AU - Yoshihiro TSUKAHARA
AU - Yukio IKEDA
AU - Yasushi ITOH
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2002
AB - A 4-12 GHz 2 W GaAs HFET amplifier has been developed. It employs two novel circuit design techniques. One is a pre-matching circuit for dual gate-bias feed. It is comprised of two shunt LCR circuits, which makes dual gate-bias feed possible. The other one is a tapered power splitting/combining FET (tapered PS/PC FET), which makes amplitude and phase imbalance between FET cells small over a wide bandwidth. In this paper, the schematic diagram and impedance characteristic of the pre-matching circuit for dual gate-bias feed are described first, showing the conditions that the impedance of FETs becomes purely resistive. Then the amplitude and phase imbalance between FET cells are compared by electromagnetic simulation for both the conventional and tapered PS/PC FETs, demonstrating that the tapered PS/PC FET has smaller amplitude and phase imbalance. Furthermore, the MSG/MAG are compared by experiment for both FETs, confirming that the tapered PS/PC FET has higher MSG/MAG. Finally, the design, fabrication, and performance of the 4-12 GHz 2 W GaAs HFET amplifier using the pre-matching circuit for dual gate-bias feed and tapered PS/PC FETs are presented to make sure that two novel circuit design techniques introduced in this paper are useful for the design of wideband lossy match power amplifiers.
ER -