IEICE TRANSACTIONS on Electronics
A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications
Summary :
A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E85-C No.2 pp.253-262
- Publication Date
- 2002/02/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section INVITED PAPER (Special Issue on High-Performance and Low-Power Microprocessors)
- Category
Authors
Tetsuya YAMADA
Makoto ISHIKAWA
Yuji OGATA
Takanobu TSUNODA
Takahiro IRITA
Saneaki TAMAKI
Kunihiko NISHIYAMA
Tatsuya KAMEI
Ken TATEZAWA
Fumio ARAKAWA
Takuichiro NAKAZAWA
Toshihiro HATTORI
Kunio UCHIYAMA
Keyword
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Tetsuya YAMADA, Makoto ISHIKAWA, Yuji OGATA, Takanobu TSUNODA, Takahiro IRITA, Saneaki TAMAKI, Kunihiko NISHIYAMA, Tatsuya KAMEI, Ken TATEZAWA, Fumio ARAKAWA, Takuichiro NAKAZAWA, Toshihiro HATTORI, Kunio UCHIYAMA, "A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 253-262, February 2002, doi: .
Abstract: A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_253/_p
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@ARTICLE{e85-c_2_253,
author={Tetsuya YAMADA, Makoto ISHIKAWA, Yuji OGATA, Takanobu TSUNODA, Takahiro IRITA, Saneaki TAMAKI, Kunihiko NISHIYAMA, Tatsuya KAMEI, Ken TATEZAWA, Fumio ARAKAWA, Takuichiro NAKAZAWA, Toshihiro HATTORI, Kunio UCHIYAMA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications},
year={2002},
volume={E85-C},
number={2},
pages={253-262},
abstract={A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.},
keywords={},
doi={},
ISSN={},
month={February},}
Copy
TY - JOUR
TI - A Low-Power Embedded RISC Microprocessor with an Integrated DSP for Mobile Applications
T2 - IEICE TRANSACTIONS on Electronics
SP - 253
EP - 262
AU - Tetsuya YAMADA
AU - Makoto ISHIKAWA
AU - Yuji OGATA
AU - Takanobu TSUNODA
AU - Takahiro IRITA
AU - Saneaki TAMAKI
AU - Kunihiko NISHIYAMA
AU - Tatsuya KAMEI
AU - Ken TATEZAWA
AU - Fumio ARAKAWA
AU - Takuichiro NAKAZAWA
AU - Toshihiro HATTORI
AU - Kunio UCHIYAMA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - A 32-bit embedded RISC microprocessor core integrating a DSP has been developed using a 0.18-µm five-layer-metal CMOS technology. The integrated DSP has a single-MAC and exploits CPU resources to reduce hardware. The DSP occupies only 0.5 mm2. The processor core includes a large on-chip 128 kB SRAM called U-memory. A large capacity on-chip memory decreases the amount of traffic with an external memory. And it is effective for low-power and high-performance operation. To realize low-power dissipation for the U-memory access, the active ratio of U-memory's access is reduced. The critical path is a load path from the U-memory, and we optimized the path through the whole chip. The chip achieves 0.79 mA/MHz executing Dhrystone 1.1 at 108 MHz, which is suitable for mobile applications.
ER -
English
